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[AMD Official Use Only]
Plan is to now commence with VEGA20 implementation and then continue to transfer other platforms after that patch is RB'd
Thanks
Darren
From: Alex Deucher <alexdeucher@xxxxxxxxx>
Sent: Wednesday, February 23, 2022 11:11 PM To: Powell, Darren <Darren.Powell@xxxxxxx> Cc: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Subject: Re: [PATCH v3 0/3] amdgpu/pm: Implement parallel sysfs_emit solution for navi10 On Tue, Jan 25, 2022 at 11:55 PM Darren Powell <darren.powell@xxxxxxx> wrote:
> > == Description == > Scnprintf use within the kernel is not recommended, but simple sysfs_emit replacement has > not been successful due to the page alignment requirement of the function. This patch > set implements a new api "emit_clock_levels" to facilitate passing both the base and > offset to the device rather than just the write pointer. > This patch is only implemented for navi10 for some clocks to seek comment on the > implementation before extending the implementation to other clock values and devices. Were you planning to extend this to other asics? Alex > > Needs to be verified on a platform that supports the overclocking > > (v3) > Rewrote patchset to order patches as (API, hw impl, usecase) > (v2) > Update to apply on commit 801771de03 > adjust printing of empty carriage return only if size == 0 > change return from amdgpu_dpm_emit_clock_levels if emit_clock_levels not found > > == Patch Summary == > linux: (git@xxxxxxxxxxxxxxxxxxxxxx:agd5f) origin/amd-staging-drm-next @ 28907fd9e048 > + f3c1d971ea17 amdgpu/pm: Implement new API function "emit" that accepts buffer base and write offset > + c67ac3384682 amdgpu/pm: Implemention of emit_clk_levels for navi10 that accepts buffer base and write offset > + 734cca28fed3 amdgpu/pm: Linked emit_clock_levels to use cases amdgpu_get_pp_{dpm_clock,od_clk_voltage} > > == System Summary == > * DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2) > + ISO(Ubuntu 20.04.3 LTS) > + Kernel(5.13.0-fdoagd5f-20220112-g28907fd9e0) > > == Test == > LOGFILE=pp_clk.test.log > AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` > AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` > HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} > > lspci -nn | grep "VGA\|Display" > $LOGFILE > FILES="pp_od_clk_voltage > pp_dpm_sclk > pp_dpm_mclk > pp_dpm_pcie > pp_dpm_socclk > pp_dpm_fclk > pp_dpm_dcefclk > pp_dpm_vclk > pp_dpm_dclk " > > for f in $FILES > do > echo === $f === >> $LOGFILE > cat $HWMON_DIR/device/$f >> $LOGFILE > done > cat $LOGFILE > > Darren Powell (3): > amdgpu/pm: Implement new API function "emit" that accepts buffer base > and write offset > amdgpu/pm: Implemention of emit_clk_levels for navi10 that accepts > buffer base and write offset > amdgpu/pm: Linked emit_clock_levels to use cases > amdgpu_get_pp_{dpm_clock,od_clk_voltage} > > .../gpu/drm/amd/include/kgd_pp_interface.h | 1 + > drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 21 ++ > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 49 +++-- > drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 4 + > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 42 +++- > drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 14 ++ > .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 188 ++++++++++++++++++ > 7 files changed, 300 insertions(+), 19 deletions(-) > > > base-commit: 28907fd9e04859fab86a143271d29ff0ff043154 > -- > 2.34.1 > |
