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[Public]
Please be sure to test this on other asics which use the HDP 4.0 code. I don't think this field exists for all of them.
Alex
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Xiaogang.Chen <xiaogang.chen@xxxxxxx>
Sent: Monday, February 21, 2022 6:05 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Cc: Chen, Xiaogang <Xiaogang.Chen@xxxxxxx> Subject: [PATCH] drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK to fix applications running across multiple GPU config hang. From: Xiaogang Chen <xiaogang.chen@xxxxxxx>
Signed-off-by: Xiaogang Chen <xiaogang.chen@xxxxxxx> --- drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 1 + drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c index d7811e0327cb..aa2c7c3f721f 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c @@ -145,6 +145,7 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev) } WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); + WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2); WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h index 25e28691d62d..65c91b0102e4 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h @@ -104,6 +104,7 @@ #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb +#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 @@ -118,6 +119,7 @@ #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L #define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L +#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000c000L #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L -- 2.25.1 |
