[AMD Official Use Only]
+Shaoyun
-----Original Message-----
From: Zhang, Bokun <Bokun.Zhang@xxxxxxx>
Sent: Monday, February 14, 2022 4:09 PM
To: Skvortsov, Victor <Victor.Skvortsov@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Skvortsov, Victor <Victor.Skvortsov@xxxxxxx>
Subject: RE: [PATCH] drm/amdgpu: Fix wait for RLCG command completion
[AMD Official Use Only]
Tested-by: Bokun Zhang <bokun.zhang@xxxxxxx>
The test configuration is 8VF with 100 loops of VM reboot.
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Victor Skvortsov
Sent: Thursday, February 3, 2022 4:25 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Skvortsov, Victor <Victor.Skvortsov@xxxxxxx>
Subject: [PATCH] drm/amdgpu: Fix wait for RLCG command completion
if (!(tmp & flag)) condition will always evaluate to true when the flag is 0x0 (AMDGPU_RLCG_GC_WRITE). Instead check that address bits are cleared to determine whether the command is complete.
Signed-off-by: Victor Skvortsov <victor.skvortsov@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index e1288901beb6..a8babe3bccb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -902,7 +902,7 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
for (i = 0; i < timeout; i++) {
tmp = readl(scratch_reg1);
- if (!(tmp & flag))
+ if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK))
break;
udelay(10);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 40803aab136f..68f592f0e992 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -43,6 +43,8 @@
#define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000
#define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000
+#define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF
+
/* all asic after AI use this offset */ #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
/* tonga/fiji use this offset */
--
2.25.1
