Re: [PATCHv2 1/3] drm/amdkfd: Fix TLB flushing in KFD SVM with no HWS

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Am 2022-02-07 um 14:52 schrieb Mukul Joshi:
With no HWS, TLB flushing will not work in SVM code.
Fix this by calling kfd_flush_tlb() which works for both
HWS and no HWS case.

Signed-off-by: Mukul Joshi <mukul.joshi@xxxxxxx>
Reviewed-by: Philip Yang <Philip.Yang@xxxxxxx>
---
v1->v2:
- Don't pass adev to svm_range_map_to_gpu().
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 24 ++++++++++--------------
  1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 41f03d165bad..058f85b432b0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1229,18 +1229,17 @@ svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start,
  			if (r)
  				break;
  		}
-		amdgpu_amdkfd_flush_gpu_tlb_pasid(pdd->dev->adev,
-					p->pasid, TLB_FLUSH_HEAVYWEIGHT);
+		kfd_flush_tlb(pdd, TLB_FLUSH_HEAVYWEIGHT);
  	}
return r;
  }
static int
-svm_range_map_to_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-		     struct svm_range *prange, unsigned long offset,
-		     unsigned long npages, bool readonly, dma_addr_t *dma_addr,
-		     struct amdgpu_device *bo_adev, struct dma_fence **fence)
+svm_range_map_to_gpu(struct kfd_process_device *pdd, struct svm_range *prange,
+		     unsigned long offset, unsigned long npages, bool readonly,
+		     dma_addr_t *dma_addr, struct amdgpu_device *bo_adev,
+		     struct dma_fence **fence)
  {
  	bool table_freed = false;
  	uint64_t pte_flags;
@@ -1248,6 +1247,8 @@ svm_range_map_to_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  	int last_domain;
  	int r = 0;
  	int64_t i, j;
+	struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv);
+	struct amdgpu_device *adev = pdd->dev->adev;

Minor style nit-pick. It's more readable when longer variable declarations are at the top. Other than that, the patch is

Reviewed-by: Felix Kuehling <Felix.Kuehling@xxxxxxx>


last_start = prange->start + offset; @@ -1305,12 +1306,8 @@ svm_range_map_to_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  	if (fence)
  		*fence = dma_fence_get(vm->last_update);
- if (table_freed) {
-		struct kfd_process *p;
-
-		p = container_of(prange->svms, struct kfd_process, svms);
-		amdgpu_amdkfd_flush_gpu_tlb_pasid(adev, p->pasid, TLB_FLUSH_LEGACY);
-	}
+	if (table_freed)
+		kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY);
  out:
  	return r;
  }
@@ -1351,8 +1348,7 @@ svm_range_map_to_gpus(struct svm_range *prange, unsigned long offset,
  			continue;
  		}
- r = svm_range_map_to_gpu(pdd->dev->adev, drm_priv_to_vm(pdd->drm_priv),
-					 prange, offset, npages, readonly,
+		r = svm_range_map_to_gpu(pdd, prange, offset, npages, readonly,
  					 prange->dma_addr[gpuidx],
  					 bo_adev, wait ? &fence : NULL);
  		if (r)



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