On 2022-01-25 01:25, Fangzhi Zuo wrote:
> [Why]
> configure_dp_hpo_throttled_vcp_size() was missing promotion before, but it was covered by
> not calling the missing function hook in the old interface hpo_dp_link_encoder->funcs.
>
> Recent refactor replaces with new caller link_hwss->set_throttled_vcp_size
> which needs that hook, and that causes null ptr hang.
>
> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@xxxxxxx>
Reviewed-by: Harry Wentland <harry.wentland@xxxxxxx>
Harry
> ---
> .../display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c | 11 +++++++++++
> .../display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h | 9 ++++++---
> 2 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
> index 5065904c7833..23621ff08c90 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
> @@ -710,6 +710,16 @@ static void dcn31_hpo_dp_stream_enc_read_state(
> }
> }
>
> +static void dcn31_set_hblank_min_symbol_width(
> + struct hpo_dp_stream_encoder *enc,
> + uint16_t width)
> +{
> + struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
> +
> + REG_SET(DP_SYM32_ENC_HBLANK_CONTROL, 0,
> + HBLANK_MINIMUM_SYMBOL_WIDTH, width);
> +}
> +
> static const struct hpo_dp_stream_encoder_funcs dcn30_str_enc_funcs = {
> .enable_stream = dcn31_hpo_dp_stream_enc_enable_stream,
> .dp_unblank = dcn31_hpo_dp_stream_enc_dp_unblank,
> @@ -725,6 +735,7 @@ static const struct hpo_dp_stream_encoder_funcs dcn30_str_enc_funcs = {
> .dp_audio_enable = dcn31_hpo_dp_stream_enc_audio_enable,
> .dp_audio_disable = dcn31_hpo_dp_stream_enc_audio_disable,
> .read_state = dcn31_hpo_dp_stream_enc_read_state,
> + .set_hblank_min_symbol_width = dcn31_set_hblank_min_symbol_width,
> };
>
> void dcn31_hpo_dp_stream_encoder_construct(
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
> index 70b94fc25304..7c77c71591a0 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
> @@ -80,7 +80,8 @@
> SRI(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id),\
> SRI(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id),\
> SRI(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id),\
> - SRI(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id)
> + SRI(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
> + SRI(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)
>
> #define DCN3_1_HPO_DP_STREAM_ENC_REGS \
> uint32_t DP_STREAM_MAPPER_CONTROL0;\
> @@ -116,7 +117,8 @@
> uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL11;\
> uint32_t DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL;\
> uint32_t DP_SYM32_ENC_SDP_AUDIO_CONTROL0;\
> - uint32_t DP_SYM32_ENC_VID_CRC_CONTROL
> + uint32_t DP_SYM32_ENC_VID_CRC_CONTROL;\
> + uint32_t DP_SYM32_ENC_HBLANK_CONTROL
>
>
> #define DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh)\
> @@ -202,7 +204,8 @@
> type GSP_SOF_REFERENCE;\
> type METADATA_PACKET_ENABLE;\
> type CRC_ENABLE;\
> - type CRC_CONT_MODE_ENABLE
> + type CRC_CONT_MODE_ENABLE;\
> + type HBLANK_MINIMUM_SYMBOL_WIDTH
>
>
> struct dcn31_hpo_dp_stream_encoder_registers {
