[AMD Official Use Only]
> -----邮件原件-----
> 发件人: Zhou1, Tao <Tao.Zhou1@xxxxxxx>
> 发送时间: Thursday, January 20, 2022 11:09 AM
> 收件人: Yang, Stanley <Stanley.Yang@xxxxxxx>; amd-
> gfx@xxxxxxxxxxxxxxxxxxxxx
> 抄送: Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Clements, John
> <John.Clements@xxxxxxx>; Ziya, Mohammad zafar
> <Mohammadzafar.Ziya@xxxxxxx>; Yang, Stanley <Stanley.Yang@xxxxxxx>
> 主题: RE: [PATCH Review 1/1] drm/amdgpu: fix convert bad page retiremt
>
> [AMD Official Use Only]
>
>
>
> > -----Original Message-----
> > From: Stanley.Yang <Stanley.Yang@xxxxxxx>
> > Sent: Thursday, January 20, 2022 12:29 AM
> > To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> > Cc: Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Zhou1, Tao
> > <Tao.Zhou1@xxxxxxx>; Clements, John <John.Clements@xxxxxxx>;
> Ziya,
> > Mohammad zafar <Mohammadzafar.Ziya@xxxxxxx>; Yang, Stanley
> > <Stanley.Yang@xxxxxxx>
> > Subject: [PATCH Review 1/1] drm/amdgpu: fix convert bad page retiremt
> >
> > Pmfw read ecc info registers and store values in eccinfo_table in the
> > following order
> >
> > umc0 ch_inst 0, 1, 2 ... 7
> > umc1 ch_inst 0, 1, 2 ... 7
> > ...
> > umc3 ch_inst 0, 1, 2 ... 7
> >
> > Driver should convert eccinfo_table_idx into channel_index according
> > to channel_idx_tbe.
> [Tao]: typo, channel_idx_tbe -> channel_idx_tbl
>
> The patch is OK for me, do we also need to apply the update to umc_v8_7.c?
[Yang, Stanley] : This need to confirm the ecc info registers address definition in pmfw, it should be updated if
definition mechanism of those registers addresses are same.
>
> >
> > Change-Id: Icafe93e458912b729d2e30d655fd68be0e12124d
> > Signed-off-by: Stanley.Yang <Stanley.Yang@xxxxxxx>
> > ---
> > drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 26 ++++++++++++++--------
> ----
> > 1 file changed, 14 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> > b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> > index 526de1ca9b8d..f5a1ba7db75a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> > @@ -58,29 +58,33 @@ static inline uint32_t
> > get_umc_v6_7_channel_index(struct amdgpu_device *adev, }
> >
> > static void umc_v6_7_ecc_info_query_correctable_error_count(struct
> > amdgpu_device *adev,
> > - uint32_t channel_index,
> > + uint32_t umc_inst, uint32_t
> > ch_inst,
> > unsigned long *error_count)
> > {
> > uint64_t mc_umc_status;
> > + uint32_t eccinfo_table_idx;
> > struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
> >
> > + eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num +
> ch_inst;
> > /* check for SRAM correctable error
> > MCUMC_STATUS is a 64 bit register */
> > - mc_umc_status = ras-
> >umc_ecc.ecc[channel_index].mca_umc_status;
> > + mc_umc_status = ras-
> > >umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
> > if (REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
> > REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
> > *error_count += 1;
> > }
> >
> > static void umc_v6_7_ecc_info_querry_uncorrectable_error_count(struct
> > amdgpu_device *adev,
> > - uint32_t channel_index,
> > + uint32_t umc_inst,
> > uint32_t ch_inst,
> > unsigned long
> *error_count) {
> > uint64_t mc_umc_status;
> > + uint32_t eccinfo_table_idx;
> > struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
> >
> > + eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num +
> ch_inst;
> > /* check the MCUMC_STATUS */
> > - mc_umc_status = ras-
> >umc_ecc.ecc[channel_index].mca_umc_status;
> > + mc_umc_status = ras-
> > >umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
> > if ((REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
> > (REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
> > REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || @@ -97,19 +101,15
> @@ static
> > void umc_v6_7_ecc_info_query_ras_error_count(struct amdgpu_device
> > *adev,
> >
> > uint32_t umc_inst = 0;
> > uint32_t ch_inst = 0;
> > - uint32_t channel_index = 0;
> >
> > /*TODO: driver needs to toggle DF Cstate to ensure
> > * safe access of UMC registers. Will add the protection */
> > LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
> > - channel_index = get_umc_v6_7_channel_index(adev,
> > - umc_inst,
> > - ch_inst);
> > umc_v6_7_ecc_info_query_correctable_error_count(adev,
> > - channel_index,
> > + umc_inst, ch_inst,
> > &(err_data->ce_count));
> >
> umc_v6_7_ecc_info_querry_uncorrectable_error_count(adev,
> > - channel_index,
> > + umc_inst, ch_inst,
> > &(err_data-
> > >ue_count));
> > }
> > }
> > @@ -122,12 +122,14 @@ static void
> > umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
> > uint64_t mc_umc_status, err_addr, retired_page;
> > struct eeprom_table_record *err_rec;
> > uint32_t channel_index;
> > + uint32_t eccinfo_table_idx;
> > struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
> >
> > + eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num +
> ch_inst;
> > channel_index =
> > adev->umc.channel_idx_tbl[umc_inst * adev-
> > >umc.channel_inst_num + ch_inst];
> >
> > - mc_umc_status = ras-
> >umc_ecc.ecc[channel_index].mca_umc_status;
> > + mc_umc_status = ras-
> > >umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
> >
> > if (mc_umc_status == 0)
> > return;
> > @@ -142,7 +144,7 @@ static void
> > umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
> > (REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
> > REG_GET_FIELD(mc_umc_status,
> > MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
> >
> > - err_addr = ras-
> >umc_ecc.ecc[channel_index].mca_umc_addr;
> > + err_addr = ras-
> > >umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
> > err_addr = REG_GET_FIELD(err_addr,
> > MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
> >
> > /* translate umc channel address to soc pa, 3 parts are
> included */
> > --
> > 2.17.1
