From: Jimmy Kizito <Jimmy.Kizito@xxxxxxx>
[Why]
According to the USB4 specification, FEC and DSC should be disabled
when a USB4 DPIA operates in TBT3 compatibility mode.
[How]
Upon detecting that a USB4 DPIA is connected to a device that is known
to operate in TBT3 mode, disable FEC and DSC support if they have been
reported by the TBT3 device.
Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@xxxxxxx>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@xxxxxxx>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@xxxxxxx>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 +
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 22 +++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dc.h | 13 ++++++-----
drivers/gpu/drm/amd/display/dc/dc_link.h | 2 ++
.../amd/display/include/ddc_service_types.h | 2 ++
5 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 5396a19eeebc..6bef6724a700 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -806,6 +806,7 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
link->type == dc_connection_mst_branch &&
link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
+ link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
link->wa_flags.dpia_mst_dsc_always_on = true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 5cc8c2633558..b3b75a98beaa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5550,6 +5550,28 @@ static bool retrieve_link_cap(struct dc_link *link)
link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
#endif
+
+ /* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode
+ * only if required.
+ */
+ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+ !link->dc->debug.dpia_debug.bits.disable_force_tbt3_work_around &&
+#endif
+ link->dpcd_caps.is_branch_dev &&
+ link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
+ link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
+ (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE ||
+ link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) {
+ /* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA.
+ * Clear FEC and DSC capabilities as a work around if that is not the case.
+ */
+ link->wa_flags.dpia_forced_tbt3_mode = true;
+ memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps));
+ memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
+ DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index);
+ } else
+ link->wa_flags.dpia_forced_tbt3_mode = false;
}
if (!dpcd_read_sink_ext_caps(link))
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5ba6abdbd3aa..14abba495f4a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -519,12 +519,13 @@ union root_clock_optimization_options {
union dpia_debug_options {
struct {
- uint32_t disable_dpia:1;
- uint32_t force_non_lttpr:1;
- uint32_t extend_aux_rd_interval:1;
- uint32_t disable_mst_dsc_work_around:1;
- uint32_t hpd_delay_in_ms:12;
- uint32_t reserved:16;
+ uint32_t disable_dpia:1; /* bit 0 */
+ uint32_t force_non_lttpr:1; /* bit 1 */
+ uint32_t extend_aux_rd_interval:1; /* bit 2 */
+ uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
+ uint32_t hpd_delay_in_ms:12; /* bits 4-15 */
+ uint32_t disable_force_tbt3_work_around:1; /* bit 16 */
+ uint32_t reserved:15;
} bits;
uint32_t raw;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index c0e37ad0e26c..704323654468 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -197,6 +197,8 @@ struct dc_link {
bool dp_mot_reset_segment;
/* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */
bool dpia_mst_dsc_always_on;
+ /* Forced DPIA into TBT3 compatibility mode. */
+ bool dpia_forced_tbt3_mode;
} wa_flags;
struct link_mst_stream_allocation_table mst_stream_alloc_table;
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index a2b80514d83e..57f92bd2814f 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -34,6 +34,8 @@
#define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24
#define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C
#define DP_BRANCH_DEVICE_ID_006037 0x006037
+#define DP_BRANCH_HW_REV_10 0x10
+#define DP_BRANCH_HW_REV_20 0x20
#define DP_DEVICE_ID_38EC11 0x38EC11
enum ddc_result {
--
2.25.1
