RE: [PATCH V3 12/12] drm/amdgpu: Removed redundant ras code

["Zhang, Hawking" <Hawking.Zhang@xxxxxxx>]

[AMD Official Use Only]

Thank you Thomas. V3 looks good to me. @Zhou1, Tao/@Clements, John/@Yang, Stanley please also take a look and raise concern if any.

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of yipechai
Sent: Wednesday, December 29, 2021 14:32
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Zhou1, Tao <Tao.Zhou1@xxxxxxx>; Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Clements, John <John.Clements@xxxxxxx>; Chai, Thomas <YiPeng.Chai@xxxxxxx>; Chai, Thomas <YiPeng.Chai@xxxxxxx>
Subject: [PATCH V3 12/12] drm/amdgpu: Removed redundant ras code

Removed redundant ras code.

Signed-off-by: yipechai <YiPeng.Chai@xxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 82 ++++++-------------------
 1 file changed, 20 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 21765e05b003..17de79be6d8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -910,51 +910,23 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
                return -EINVAL;

        block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
+       if (!block_obj || !block_obj->hw_ops)   {
+               dev_info(adev->dev, "%s doesn't config ras function \n",
+                       get_ras_block_str(&info->head));
+               return -EINVAL;
+       }

-       switch (info->head.block) {
-       case AMDGPU_RAS_BLOCK__UMC:
-               if (!block_obj || !block_obj->hw_ops)   {
-                       dev_info(adev->dev, "%s doesn't config ras function \n",
-                               get_ras_block_str(&info->head));
-                       return -EINVAL;
-               }
+       if (block_obj->hw_ops->query_ras_error_count)
+               block_obj->hw_ops->query_ras_error_count(adev, &err_data);

-               if (block_obj->hw_ops->query_ras_error_count)
-                       block_obj->hw_ops->query_ras_error_count(adev, &err_data);
-               /* umc query_ras_error_address is also responsible for clearing
-                * error status
-                */
-               if (block_obj->hw_ops->query_ras_error_address)
-                       block_obj->hw_ops->query_ras_error_address(adev, &err_data);
-               break;
-       case AMDGPU_RAS_BLOCK__SDMA:
-       case AMDGPU_RAS_BLOCK__GFX:
-       case AMDGPU_RAS_BLOCK__MMHUB:
-               if (!block_obj || !block_obj->hw_ops)   {
-                       dev_info(adev->dev, "%s doesn't config ras function \n",
-                                               get_ras_block_str(&info->head));
-                       return -EINVAL;
-               }
-               if (block_obj->hw_ops->query_ras_error_count)
-                       block_obj->hw_ops->query_ras_error_count(adev, &err_data);
+       if (info->head.block == AMDGPU_RAS_BLOCK__UMC)
+               block_obj->hw_ops->query_ras_error_address(adev, &err_data);

+       if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
+           (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
+           (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
                if (block_obj->hw_ops->query_ras_error_status)
                        block_obj->hw_ops->query_ras_error_status(adev);
-               break;
-       case AMDGPU_RAS_BLOCK__PCIE_BIF:
-       case AMDGPU_RAS_BLOCK__XGMI_WAFL:
-       case AMDGPU_RAS_BLOCK__HDP:
-       case AMDGPU_RAS_BLOCK__MCA:
-               if (!block_obj || !block_obj->hw_ops)   {
-                       dev_info(adev->dev, "%s doesn't config ras function \n",
-                               get_ras_block_str(&info->head));
-                       return -EINVAL;
-               }
-               if (block_obj->hw_ops->query_ras_error_count)
-                       block_obj->hw_ops->query_ras_error_count(adev, &err_data);
-               break;
-       default:
-               break;
        }

        obj->err_data.ue_count += err_data.ue_count; @@ -1016,32 +988,18 @@ int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
        if (!amdgpu_ras_is_supported(adev, block))
                return -EINVAL;

-       switch (block) {
-       case AMDGPU_RAS_BLOCK__GFX:
-       case AMDGPU_RAS_BLOCK__MMHUB:
-               if (!block_obj || !block_obj->hw_ops)   {
-                       dev_info(adev->dev, "%s doesn't config ras function \n", ras_block_str(block));
-                       return -EINVAL;
-               }
+       if (!block_obj || !block_obj->hw_ops)   {
+               dev_info(adev->dev, "%s doesn't config ras function \n", ras_block_str(block));
+               return -EINVAL;
+       }

-               if (block_obj->hw_ops->reset_ras_error_count)
-                       block_obj->hw_ops->reset_ras_error_count(adev);
+       if (block_obj->hw_ops->reset_ras_error_count)
+               block_obj->hw_ops->reset_ras_error_count(adev);

+       if ((block == AMDGPU_RAS_BLOCK__GFX) ||
+           (block == AMDGPU_RAS_BLOCK__MMHUB)) {
                if (block_obj->hw_ops->reset_ras_error_status)
                        block_obj->hw_ops->reset_ras_error_status(adev);
-               break;
-       case AMDGPU_RAS_BLOCK__SDMA:
-       case AMDGPU_RAS_BLOCK__HDP:
-               if (!block_obj || !block_obj->hw_ops)   {
-                       dev_info(adev->dev, "%s doesn't config ras function \n", ras_block_str(block));
-                       return -EINVAL;
-               }
-
-               if (block_obj->hw_ops->reset_ras_error_count)
-                       block_obj->hw_ops->reset_ras_error_count(adev);
-               break;
-       default:
-               break;
        }

        return 0;
--
2.25.1