Re: [PATCH 2/5] drm/amdgpu: Modify indirect register access for gmc_v9_0 sriov

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I don't know what others may think, but this coding while correct:

-               WREG32_NO_KIQ(hub->vm_inv_eng0_req +
-                             hub->eng_distance * eng, inv_req);
+               (vmhub == AMDGPU_GFXHUB_0) ?
+                       WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req) :
+                       WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);

if is bit difficult to read. I wouldn't mind if the results of those function calls were stored in a variable, but here, you are using it as an if/else or a switch statement. It is better to do it like that:

switch(vmhub) {
case AMDGPU_GFXHUB_0):
//yadayada

or

if (vmhub == AMDGPU_GFXHUB_0) 
 //yadayada
else {
 // yada du
}

From: Skvortsov, Victor <Victor.Skvortsov@xxxxxxx>
Sent: Wednesday, December 15, 2021 10:55 AM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>; Deng, Emily <Emily.Deng@xxxxxxx>; Liu, Monk <Monk.Liu@xxxxxxx>; Ming, Davis <Davis.Ming@xxxxxxx>; Liu, Shaoyun <Shaoyun.Liu@xxxxxxx>; Zhou, Peng Ju <PengJu.Zhou@xxxxxxx>; Chen, JingWen <JingWen.Chen2@xxxxxxx>; Chen, Horace <Horace.Chen@xxxxxxx>; Nieto, David M <David.Nieto@xxxxxxx>
Cc: Skvortsov, Victor <Victor.Skvortsov@xxxxxxx>
Subject: [PATCH 2/5] drm/amdgpu: Modify indirect register access for gmc_v9_0 sriov
 
Modify GC register access from MMIO to RLCG if the
indirect flag is set

Signed-off-by: Victor Skvortsov <victor.skvortsov@xxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 45 +++++++++++++++++++--------
 1 file changed, 32 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index db2ec84f7237..345ce7fc6463 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -478,9 +478,16 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                         hub = &adev->vmhub[j];
                         for (i = 0; i < 16; i++) {
                                 reg = hub->vm_context0_cntl + i;
-                               tmp = RREG32(reg);
+
+                               tmp = (j == AMDGPU_GFXHUB_0) ?
+                                       RREG32_SOC15_IP(GC, reg) :
+                                       RREG32_SOC15_IP(MMHUB, reg);
+
                                 tmp &= ~bits;
-                               WREG32(reg, tmp);
+
+                               (j == AMDGPU_GFXHUB_0) ?
+                                       WREG32_SOC15_IP(GC, reg, tmp) :
+                                       WREG32_SOC15_IP(MMHUB, reg, tmp);
                         }
                 }
                 break;
@@ -489,9 +496,16 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                         hub = &adev->vmhub[j];
                         for (i = 0; i < 16; i++) {
                                 reg = hub->vm_context0_cntl + i;
-                               tmp = RREG32(reg);
+
+                               tmp = (j == AMDGPU_GFXHUB_0) ?
+                                       RREG32_SOC15_IP(GC, reg) :
+                                       RREG32_SOC15_IP(MMHUB, reg);
+
                                 tmp |= bits;
-                               WREG32(reg, tmp);
+
+                               (j == AMDGPU_GFXHUB_0) ?
+                                       WREG32_SOC15_IP(GC, reg, tmp) :
+                                       WREG32_SOC15_IP(MMHUB, reg, tmp);
                         }
                 }
                 break;
@@ -789,8 +803,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
         if (use_semaphore) {
                 for (j = 0; j < adev->usec_timeout; j++) {
                         /* a read return value of 1 means semaphore acuqire */
-                       tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
-                                           hub->eng_distance * eng);
+                       tmp = (vmhub == AMDGPU_GFXHUB_0) ?
+                                       RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng) :
+                                       RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
                         if (tmp & 0x1)
                                 break;
                         udelay(1);
@@ -801,8 +816,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
         }
 
         do {
-               WREG32_NO_KIQ(hub->vm_inv_eng0_req +
-                             hub->eng_distance * eng, inv_req);
+               (vmhub == AMDGPU_GFXHUB_0) ?
+                       WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req) :
+                       WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
 
                 /*
                  * Issue a dummy read to wait for the ACK register to
@@ -815,8 +831,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
                                       hub->eng_distance * eng);
 
                 for (j = 0; j < adev->usec_timeout; j++) {
-                       tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
-                                           hub->eng_distance * eng);
+                       tmp = (vmhub == AMDGPU_GFXHUB_0) ?
+                               RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng) :
+                               RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
                         if (tmp & (1 << vmid))
                                 break;
                         udelay(1);
@@ -827,13 +844,15 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
         } while (inv_req);
 
         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
-       if (use_semaphore)
+       if (use_semaphore) {
                 /*
                  * add semaphore release after invalidation,
                  * write with 0 means semaphore release
                  */
-               WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
-                             hub->eng_distance * eng, 0);
+               (vmhub == AMDGPU_GFXHUB_0) ?
+                       WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0) :
+                       WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0);
+       }
 
         spin_unlock(&adev->gmc.invalidate_lock);
 
--
2.25.1


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