On 2021-12-07 10:07, Nicholas Kazlauskas wrote:
> [Why]
> During dcn31_stream_encoder_create, if PHYC/D get remapped to F/G on B0
> then we'll index 5 or 6 into a array of length 5 - leading to an
> access violation on some configs during device creation.
>
> [How]
> Software won't be touching PHYF/PHYG directly, so just extend the
> array to cover all possible engine IDs.
>
> Even if it does by try to access one of these registers by accident
> the offset will be 0 and we'll get a warning during the access.
>
> Fixes: 2fe9a0e1173f ("drm/amd/display: Fix DCN3 B0 DP Alt Mapping")
> Cc: Mario Limonciello <mario.limonciello@xxxxxxx>
> Cc: Harry Wentland <harry.wentland@xxxxxxx>
> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@xxxxxxx>
Reviewed-by: Harry Wentland <harry.wentland@xxxxxxx>
Harry
> ---
> drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> index ec5b4cec0ef2..04b52c9d18da 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> @@ -485,7 +485,8 @@ static const struct dcn31_apg_mask apg_mask = {
> SE_DCN3_REG_LIST(id)\
> }
>
> -static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
> +/* Some encoders won't be initialized here - but they're logical, not physical. */
> +static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
> stream_enc_regs(0),
> stream_enc_regs(1),
> stream_enc_regs(2),
>
