[AMD Official Use Only]
Reviewed-by: Evan Quan <evan.quan@xxxxxxx>
> -----Original Message-----
> From: Lazar, Lijo <Lijo.Lazar@xxxxxxx>
> Sent: Monday, November 15, 2021 3:42 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Zhang, Hawking
> <Hawking.Zhang@xxxxxxx>; Wang, Yang(Kevin)
> <KevinYang.Wang@xxxxxxx>; Quan, Evan <Evan.Quan@xxxxxxx>
> Subject: [PATCH] drm/amd/pm: Remove artificial freq level on Navi1x
>
> Print Navi1x fine grained clocks in a consistent manner with other SOCs.
> Don't show aritificial DPM level when the current clock equals min or max.
>
> Signed-off-by: Lijo Lazar <lijo.lazar@xxxxxxx>
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 71161f6b78fe..60a557068ea4 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -1265,7 +1265,7 @@ static int navi10_print_clk_levels(struct
> smu_context *smu,
> enum smu_clk_type clk_type, char *buf) {
> uint16_t *curve_settings;
> - int i, size = 0, ret = 0;
> + int i, levels, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> uint32_t freq_values[3] = {0};
> uint32_t mark_index = 0;
> @@ -1319,14 +1319,17 @@ static int navi10_print_clk_levels(struct
> smu_context *smu,
> freq_values[1] = cur_value;
> mark_index = cur_value == freq_values[0] ? 0 :
> cur_value == freq_values[2] ? 2 : 1;
> - if (mark_index != 1)
> - freq_values[1] = (freq_values[0] +
> freq_values[2]) / 2;
>
> - for (i = 0; i < 3; i++) {
> + levels = 3;
> + if (mark_index != 1) {
> + levels = 2;
> + freq_values[1] = freq_values[2];
> + }
> +
> + for (i = 0; i < levels; i++) {
> size += sysfs_emit_at(buf, size,
> "%d: %uMhz %s\n", i, freq_values[i],
> i == mark_index ? "*" : "");
> }
> -
> }
> break;
> case SMU_PCIE:
> --
> 2.17.1
