RE: [PATCH 00/33] DC Patches October 24, 2020

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Hi all,
 
This week this patchset was tested on the following systems:
 
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
 
AMD Ryzen 9 5900H, with the following display types: eDP 1080p 60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
 
Sapphire Pulse RX5700XT with the following display types:
4k 60hz  (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
 
Reference AMD RX6800 with the following display types:
4k 60hz  (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
 
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems. Also tested DSC via USB-C to DP DSC Hub with 3x 4k 60hz on Ryzen 9 5900h and Ryzen 5 4500u.
 
 
Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
 
 
Thank you,
 
Dan Wheeler
Technologist  |  AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
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-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Rodrigo Siqueira
Sent: October 24, 2021 9:31 AM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Wentland, Harry <Harry.Wentland@xxxxxxx>; Li, Sun peng (Leo) <Sunpeng.Li@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Pillai, Aurabindo <Aurabindo.Pillai@xxxxxxx>; Zhuo, Qingqing <Qingqing.Zhuo@xxxxxxx>; Lipski, Mikita <Mikita.Lipski@xxxxxxx>; Li, Roman <Roman.Li@xxxxxxx>; Jacob, Anson <Anson.Jacob@xxxxxxx>; Lin, Wayne <Wayne.Lin@xxxxxxx>; Wang, Chao-kai (Stylon) <Stylon.Wang@xxxxxxx>; Chiu, Solomon <Solomon.Chiu@xxxxxxx>; Kotarac, Pavle <Pavle.Kotarac@xxxxxxx>; Gutierrez, Agustin <Agustin.Gutierrez@xxxxxxx>
Subject: [PATCH 00/33] DC Patches October 24, 2020

This new DC version brings improvements in the following areas:
- Improvements for USB4;
- Isolate FPU code for DCN20, DCN301, and DSC;
- Fixes on Linking training;
- Refactoring some parts of the code, such as PSR;

Thanks

Ahmad Othman (2):
  drm/amd/display: Add support for USB4 on C20 PHY for DCN3.1
  drm/amd/display: fix a crash on USB4 over C20 PHY

Anson Jacob (2):
  drm/amd/display: dcn20_resource_construct reduce scope of FPU enabled
  drm/amd/display: Remove unused macros

Anthony Koo (2):
  drm/amd/display: [FW Promotion] Release 0.0.89
  drm/amd/display: [FW Promotion] Release 0.0.90

Aric Cyr (4):
  drm/amd/display: Handle I2C-over-AUX write channel status update
  drm/amd/display: 3.2.158
  drm/amd/display: Fix 3DLUT skipped programming
  drm/amd/display: 3.2.159

Dmytro Laktyushkin (3):
  drm/amd/display: clean up dcn31 revision check
  drm/amd/display: restyle dcn31 resource header inline with other asics
  drm/amd/display: allow windowed mpo + odm

George Shen (2):
  drm/amd/display: Implement fixed DP drive settings
  drm/amd/display: Add comment for preferred_training_settings

Guo, Bing (2):
  drm/amd/display: Get ceiling for v_total calc
  drm/amd/display: set Layout properly for 8ch audio at timing
    validation

Hansen (1):
  drm/amd/display: Set phy_mux_sel bit in dmub scratch register

Jimmy Kizito (1):
  drm/amd/display: Add workaround flag for EDID read on certain docks

Lewis Huang (1):
  drm/amd/display: Align bw context with hw config when system resume

Martin Leung (1):
  drm/amd/display: Manually adjust strobe for DCN303

Meenakshikumar Somasundaram (2):
  drm/amd/display: FEC configuration for dpia links
  drm/amd/display: FEC configuration for dpia links in MST mode

Michael Strauss (2):
  drm/amd/display: Set i2c memory to light sleep during hw init
  drm/amd/display: Defer GAMCOR and DSCL power down sequence to vupdate

Qingqing Zhuo (2):
  drm/amd/display: move FPU associated DSC code to DML folder
  drm/amd/display: move FPU associated DCN301 code to DML folder

Robin Chen (1):
  drm/amd/display: dc_link_set_psr_allow_active refactoring

Wenjing Liu (5):
  drm/amd/display: adopt DP2.0 LT SCR revision 8
  drm/amd/display: implement decide lane settings
  drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings
  drm/amd/display: add two lane settings training options
  drm/amd/display: fix link training regression for 1 or 2 lane

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   2 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |   2 +
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  10 +-
 .../drm/amd/display/dc/bios/bios_parser2.c    |   2 +
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |  16 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  17 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 118 ++++-  .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  15 +-  .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 498 +++++++-----------
 .../drm/amd/display/dc/core/dc_link_dpia.c    |  57 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  14 +-
 drivers/gpu/drm/amd/display/dc/dc.h           |  23 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |   5 -
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  13 +-
 .../gpu/drm/amd/display/dc/dce/dce_audio.c    |   6 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  |  34 +-
 .../gpu/drm/amd/display/dc/dce/dce_hwseq.h    |   3 +-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  20 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |   1 +
 .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c |  12 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   6 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  19 +-  .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c  |  14 +
 .../drm/amd/display/dc/dcn30/dcn30_dpp_cm.c   |   8 +-
 .../drm/amd/display/dc/dcn30/dcn30_resource.c |  35 +-
 .../gpu/drm/amd/display/dc/dcn301/Makefile    |  26 -
 .../amd/display/dc/dcn301/dcn301_resource.c   | 349 +-----------
 .../amd/display/dc/dcn301/dcn301_resource.h   |   3 +
 .../amd/display/dc/dcn303/dcn303_resource.c   |  14 +
 .../display/dc/dcn31/dcn31_dio_link_encoder.c |   4 +-
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    |   5 +
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |  11 +-  .../drm/amd/display/dc/dcn31/dcn31_resource.h |  10 +
 drivers/gpu/drm/amd/display/dc/dm_cp_psp.h    |   2 +
 drivers/gpu/drm/amd/display/dc/dml/Makefile   |   6 +
 .../amd/display/dc/dml/dcn301/dcn301_fpu.c    | 390 ++++++++++++++
 .../amd/display/dc/dml/dcn301/dcn301_fpu.h    |  42 ++
 .../amd/display/dc/{ => dml}/dsc/qp_tables.h  |   0
 .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.c  | 291 ++++++++++  .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.h  |  94 ++++
 drivers/gpu/drm/amd/display/dc/dsc/Makefile   |  29 -
 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c  | 259 ---------  drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h  |  50 +-
 .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c  |   1 -
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  16 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h   |   2 +
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   |   1 +
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  55 +-
 .../gpu/drm/amd/display/dmub/src/dmub_dcn31.c |   2 +
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |   1 +
 .../display/include/grph_object_ctrl_defs.h   |   1 +
 .../amd/display/include/i2caux_interface.h    |   3 +
 .../amd/display/include/link_service_types.h  |  29 +-
 .../amd/display/modules/freesync/freesync.c   |  15 +-
 .../drm/amd/display/modules/inc/mod_hdcp.h    |   2 +
 55 files changed, 1529 insertions(+), 1134 deletions(-)  create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h
 rename drivers/gpu/drm/amd/display/dc/{ => dml}/dsc/qp_tables.h (100%)  create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h

--
2.25.1




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