Re: But the logic applied in this fix tells that anything in IP discovery (version table or harvest table) doesn't solve the problem. This is equivalent to an ASIC specific logic similar to old ASIC enum checks. Exactly, this is the challenge. Regards, Guchun -----Original Message----- From: Lazar, Lijo <Lijo.Lazar@xxxxxxx> Sent: Thursday, October 21, 2021 8:56 PM To: Chen, Guchun <Guchun.Chen@xxxxxxx>; Koenig, Christian <Christian.Koenig@xxxxxxx>; Pan, Xinhui <Xinhui.Pan@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Liu, Leo <Leo.Liu@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx Subject: Re: [PATCH] drm/amdgpu: limit VCN instance number to 1 for NAVY_FLOUNDER On 10/21/2021 6:10 PM, Chen, Guchun wrote: > Hi Lijo, > > Alex has a following fix "85db7fcb2e53 drm/amdgpu: get VCN harvest information from IP discovery table" to fix that logic. But the logic applied in this fix tells that anything in IP discovery (version table or harvest table) doesn't solve the problem. This is equivalent to an ASIC specific logic similar to old ASIC enum checks. > > For other ASCIs like DIMGREY_CAVEFISH and BEIGE_GOBY, its instance num is 1, match with VBIOS discovery table. So there is no need to handle it. > Thanks for the clarification! It looks good to me, will leave it to Alex/Leo/James. Thanks, Lijo > Regards, > Guchun > > -----Original Message----- > From: Lazar, Lijo <Lijo.Lazar@xxxxxxx> > Sent: Thursday, October 21, 2021 5:45 PM > To: Chen, Guchun <Guchun.Chen@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx; > Koenig, Christian <Christian.Koenig@xxxxxxx>; Pan, Xinhui > <Xinhui.Pan@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>; > Liu, Leo <Leo.Liu@xxxxxxx> > Subject: Re: [PATCH] drm/amdgpu: limit VCN instance number to 1 for > NAVY_FLOUNDER > > > > On 10/21/2021 12:45 PM, Guchun Chen wrote: >> VCN instance 1 is power gated permanently by SMU. >> >> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1743 >> >> Fixes: f6b6d7d6bc2d("drm/amdgpu/vcn: remove manual instance setting") > > Nice find. Looking at the fix, the logic is already broken by > 5e26e52adb46("drm/amdgpu/vcn3.0: convert to IP version checking") > > Any ASIC other than Sienna which has same VCN IP version (3.0.0) may be broken. Any more extra checks? > > Thanks, > Lijo > >> Signed-off-by: Guchun Chen <guchun.chen@xxxxxxx> >> --- >> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c >> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c >> index dbfd92984655..4848922667f2 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c >> @@ -103,6 +103,15 @@ static int vcn_v3_0_early_init(void *handle) >> adev->vcn.num_enc_rings = 0; >> else >> adev->vcn.num_enc_rings = 2; >> + >> + /* >> + * Fix ME. >> + * VCN instance number is limited to 1 for below ASIC due to >> + * VCN instnace 1 is permanently power gated. >> + */ >> + if ((adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 0)) && >> + (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) >> + adev->vcn.num_vcn_inst = 1; >> } >> >> vcn_v3_0_set_dec_ring_funcs(adev); >>
