[Public] Hi all, This week this patchset was tested on the following systems: HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA) AMD Ryzen 9 5900H, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA) Sapphire Pulse RX5700XT with the following display types: 4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA) Reference AMD RX6800 with the following display types: 4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA) Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems. Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx> Thank you, Dan Wheeler Technologist | AMD SW Display ------------------------------------------------------------------------------------------------------------------ 1 Commerce Valley Dr E, Thornhill, ON L3T 7X6 Facebook | Twitter | amd.com -----Original Message----- From: Gutierrez, Agustin <Agustin.Gutierrez@xxxxxxx> Sent: October 15, 2021 2:43 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Wentland, Harry <Harry.Wentland@xxxxxxx>; Li, Sun peng (Leo) <Sunpeng.Li@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Pillai, Aurabindo <Aurabindo.Pillai@xxxxxxx>; Zhuo, Qingqing <Qingqing.Zhuo@xxxxxxx>; Lipski, Mikita <Mikita.Lipski@xxxxxxx>; Li, Roman <Roman.Li@xxxxxxx>; Jacob, Anson <Anson.Jacob@xxxxxxx>; Lin, Wayne <Wayne.Lin@xxxxxxx>; Wang, Chao-kai (Stylon) <Stylon.Wang@xxxxxxx>; Chiu, Solomon <Solomon.Chiu@xxxxxxx>; Kotarac, Pavle <Pavle.Kotarac@xxxxxxx>; Gutierrez, Agustin <Agustin.Gutierrez@xxxxxxx>; Wheeler, Daniel <Daniel.Wheeler@xxxxxxx>; Broadworth, Mark <Mark.Broadworth@xxxxxxx> Subject: [PATCH 00/27] DC Patchset for October 15 This DC patchset brings improvements in multiple areas. In summary, we highlight: * Fix some issues such as DP2 problem, prefetch bandwidth calculation for DCN3.1 and others. * Increased Z9 latency and removed z10 save after dsc disable. * Revert a couple of bad changes. * Added missing PSR state patch. Cc: Daniel Wheeler <daniel.wheeler@xxxxxxx> Cc: Mark Broadworth <mark.broadworth@xxxxxxx> Agustin Gutierrez (2): Revert "drm/amd/display: Fix error in dmesg at boot" Revert "drm/amd/display: Add helper for blanking all dp displays" Anthony Koo (2): drm/amd/display: Change initializer to single brace drm/amd/display: [FW Promotion] Release 0.0.88 Aric Cyr (2): drm/amd/display: Validate plane rects before use drm/amd/display: 3.2.157 Eric Yang (1): drm/amd/display: increase Z9 latency to workaround underflow in Z9 Hansen (1): drm/amd/display: Fix DP2 SE and LE SYMCLK selection for B0 PHY Jake Wang (6): drm/amd/display: Disable dpp root clock when not being used drm/amd/display: Disable dsc root clock when not being used drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le drm/amd/display: Removed z10 save after dsc disable drm/amd/display: Moved dccg init to after bios golden init drm/amd/display: Disable hdmistream and hdmichar clocks Jimmy Kizito (2): drm/amd/display: Clear encoder assignment for copied streams drm/amd/display: Do not skip link training on DP quick hot plug Josip Pavic (1): drm/amd/display: do not compare integers of different widths Lai, Derek (1): drm/amd/display: Removed power down on boot from DCN31 Michael Strauss (1): drm/amd/display: Clean Up VPG Low Mem Power Mikita Lipski (1): drm/amd/display: Add missing PSR state Nevenko Stupar (1): drm/amd/display: Add bios parser support for latest firmware_info Nicholas Kazlauskas (2): drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1 drm/amd/display: Require immediate flip support for DCN3.1 planes Nikola Cornij (2): drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1 drm/amd/display: Increase watermark latencies for DCN3.1 Wenjing Liu (2): drm/amd/display: add DP2.0 debug option to set MST_EN for SST stream drm/amd/display: correct apg audio channel enable golden value .../drm/amd/display/dc/bios/bios_parser2.c | 90 ++++++- .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 21 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 10 - drivers/gpu/drm/amd/display/dc/core/dc_link.c | 63 +---- .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 32 +-- .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 9 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 5 + .../gpu/drm/amd/display/dc/core/dc_stream.c | 4 + drivers/gpu/drm/amd/display/dc/dc.h | 3 +- drivers/gpu/drm/amd/display/dc/dc_link.h | 1 - drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 + .../display/dc/dce110/dce110_hw_sequencer.c | 24 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 49 +++- .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 34 ++- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 +- .../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 39 ++- .../gpu/drm/amd/display/dc/dcn31/dcn31_apg.c | 2 +- .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 237 +++++++++++++++++- .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h | 34 ++- .../drm/amd/display/dc/dcn31/dcn31_hwseq.c | 114 +++++---- .../drm/amd/display/dc/dcn31/dcn31_resource.c | 17 +- .../dc/dml/dcn31/display_mode_vba_31.c | 6 +- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 9 + .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 2 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +- .../include/asic_reg/dcn/dcn_3_1_2_offset.h | 2 + .../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h | 8 + 29 files changed, 643 insertions(+), 185 deletions(-) -- 2.25.1
