[Public] > -----Original Message----- > From: Wentland, Harry <Harry.Wentland@xxxxxxx> > Sent: Wednesday, October 6, 2021 1:14 AM > To: Lin, Wayne <Wayne.Lin@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Kazlauskas, Nicholas <Nicholas.Kazlauskas@xxxxxxx>; Siqueira, Rodrigo > <Rodrigo.Siqueira@xxxxxxx>; Wang, Chao-kai (Stylon) <Stylon.Wang@xxxxxxx>; Shih, Jude <Jude.Shih@xxxxxxx>; Kizito, Jimmy > <Jimmy.Kizito@xxxxxxx>; Somasundaram, Meenakshikumar <Meenakshikumar.Somasundaram@xxxxxxx> > Subject: Re: [PATCH v2 00/23] USB4 DP tunneling > > On 2021-10-05 03:51, Wayne Lin wrote: > > USB4 runs over USB-C and can tunnels USB3, PCIe and DP protocols. > > > > A USB4 router is responsible for mapping Tunneled Protocol traffic to > > USB4 packets and routes packets through the USB4 Fabric. > > For this patchset, we have native DisplayPort able to be tunneled over > > USB4 Fabric. > > > > E.g. > > DP source -> DPIA (DP In Adapter) -> USB4 host router -> USB4 port -> > > USB4 device router -> DPOA (DP Out Adapter) -> DPTX -> DP sink > > > > Briefly, there is a CM (Connection Manager) in USB subsystem which > > handles relevant USB4 channel configuratons. Our DMCUB is responsible > > for interacting with CM to control DPIA to enable Video Path & AUX > > Path. Once DPIA gets into Paired state, DP source is then having a > > constructed end-to-end path to interact with DP sink as the > > conventional way. > > > > From DP Source perspective, the USB4 Fabric and the Adapters are > > either totally transparent or act as an LTTPR. Besides, due to > > constraints of USB4 protocols, AUX transactions under USB4 now is > > handled by DMCUB to meet USB4 protocol requirement. > > > > Changes since v1: > > * Give the description of rough working flow of USB4 DP tunneling > > > > Thanks for the overview. > > Is DP-over-USB4, or our implementation of it, specific to AMD HW? > > Would it make sense to deal with DP-over-USB4 core functionality in DRM core in a way that's common to all implementers? Hi Harry, In my opinion, it's just another connector interface. Like we have multiple type interfaces, HDMI/DP/VGA/Type-C (DP alt mode), and now we have new USB4 way to notify DP hotplug event. DPIA/CM relevant hotplug events handling should be USB4 scope, I think current implementation should be fine. > > Have you run checkpatch.pl on all patches? Yes, have run it. > > Patches 2-3, 9-18, 20-23 and > Patches 1, 4-8 with the suggested title/description updates and Patch 19 with the DCN guard dropped (or confirmation that it's needed) are > Acked-by: Harry Wentland <harry.wentland@xxxxxxx> > Thanks Harry! > Harry > > > --- > > > > Jimmy Kizito (14): > > drm/amd/display: Update link encoder object creation. > > drm/amd/display: Support USB4 dynamic link encoder selection. > > drm/amd/display: Support USB4 for display endpoint control path. > > drm/amd/display: Support DP tunneling when DPRX detection > > drm/amd/display: Update training parameters for DPIA links > > drm/amd/display: Support USB4 when DP link training. > > drm/amd/display: Implement DPIA training loop > > drm/amd/display: Implement DPIA link configuration > > drm/amd/display: Implement DPIA clock recovery phase > > drm/amd/display: Implement DPIA equalisation phase > > drm/amd/display: Implement end of training for hop in DPIA display > > path > > drm/amd/display: Read USB4 DP tunneling data from DPCD. > > drm/amd/display: Fix DIG_HPD_SELECT for USB4 display endpoints. > > drm/amd/display: Add debug flags for USB4 DP link training. > > > > Jude Shih (4): > > drm/amd/display: Support for SET_CONFIG processing with DMUB > > drm/amd/display: Deadlock/HPD Status/Crash Bug Fix > > drm/amd/display: Fix USB4 Aux via DMUB terminate unexpectedly > > drm/amd/display: USB4 bring up set correct address > > > > Meenakshikumar Somasundaram (5): > > drm/amd/display: USB4 DPIA enumeration and AUX Tunneling > > drm/amd/display: Support for DMUB HPD and HPD RX interrupt handling > > drm/amd/display: Support for SET_CONFIG processing with DMUB > > drm/amd/display: Add dpia debug options > > drm/amd/display: Fix for access for ddc pin and aux engine. > > > > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 106 +- > > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12 +- > > .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 17 +- > > drivers/gpu/drm/amd/display/dc/Makefile | 2 +- > > drivers/gpu/drm/amd/display/dc/core/dc.c | 179 +++- > > drivers/gpu/drm/amd/display/dc/core/dc_link.c | 81 +- > > .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 9 +- > > .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 36 +- > > .../drm/amd/display/dc/core/dc_link_dpia.c | 945 ++++++++++++++++++ > > drivers/gpu/drm/amd/display/dc/core/dc_stat.c | 8 + > > drivers/gpu/drm/amd/display/dc/dc.h | 22 + > > drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 31 + > > drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + > > drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 3 + > > .../display/dc/dcn31/dcn31_dio_link_encoder.c | 126 ++- > > .../drm/amd/display/dc/dcn31/dcn31_hwseq.c | 6 + > > .../drm/amd/display/dc/dcn31/dcn31_resource.c | 7 + > > drivers/gpu/drm/amd/display/dc/dm_helpers.h | 5 + > > .../gpu/drm/amd/display/dc/inc/core_types.h | 3 + > > .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h | 1 + > > .../gpu/drm/amd/display/dc/inc/dc_link_dpia.h | 98 ++ > > drivers/gpu/drm/amd/display/dc/inc/resource.h | 1 + > > drivers/gpu/drm/amd/display/dc/os_types.h | 1 + > > drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 3 + > > .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 113 ++- > > .../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 1 + > > .../drm/amd/display/dmub/src/dmub_srv_stat.c | 16 + > > .../gpu/drm/amd/display/include/dal_asic_id.h | 2 +- > > 28 files changed, 1793 insertions(+), 42 deletions(-) create mode > > 100644 drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c > > create mode 100644 drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h > > -- Wayne
