Re: [PATCH v2 05/23] drm/amd/display: Support USB4 for display endpoint control path.

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On 2021-10-05 03:51, Wayne Lin wrote:
> From: Jimmy Kizito <Jimmy.Kizito@xxxxxxx>
> 
> [why & how]
> Add codes for commit "79ed7354d70f drm/amd/display: Update
> display endpoint control path" to support USB4 DP tunneling
> feature.
> 

Suggested Title: "Stub out DPIA link training call"

Suggested Description:
"Add stub for DPIA link training and define new DPIA DMUB commands
to support it."

> Reviewed-by: Jun Lei <Jun.Lei@xxxxxxx>
> Acked-by: Wayne Lin <Wayne.Lin@xxxxxxx>
> Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@xxxxxxx>
> Signed-off-by: Jimmy Kizito <Jimmy.Kizito@xxxxxxx>
> ---
>  .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  30 ++++-
>  .../display/dc/dcn31/dcn31_dio_link_encoder.c | 118 +++++++++++++++++-
>  .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  41 ++++++
>  3 files changed, 182 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 649a9da338a7..4df71d728319 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -2312,6 +2312,23 @@ enum link_training_result dc_link_dp_perform_link_training(
>  	return status;
>  }
>  
> +/*
> + * Train DP tunneling link for USB4 DPIA display endpoint.
> + *
> + * DPIA equivalent of dc_link_dp_perfrorm_link_training.

/s/dc_link_dp_perfrorm_link_training/dc_link_dp_perform_link_training

Harry

> + */
> +enum link_training_result dc_link_dpia_perform_link_training(struct dc_link *link,
> +	const struct dc_link_settings *link_setting,
> +	bool skip_video_pattern)
> +{
> +	enum link_training_result status;
> +
> +	/** @todo Always fail until USB4 DPIA training implemented. */
> +	status = LINK_TRAINING_CR_FAIL_LANE0;
> +
> +	return status;
> +}
> +
>  bool perform_link_training_with_retries(
>  	const struct dc_link_settings *link_setting,
>  	bool skip_video_pattern,
> @@ -2383,10 +2400,15 @@ bool perform_link_training_with_retries(
>  			dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
>  			return true;
>  		} else {
> -				status = dc_link_dp_perform_link_training(
> -										link,
> -										&current_setting,
> -										skip_video_pattern);
> +			if (link->is_dig_mapping_flexible)
> +				status = dc_link_dpia_perform_link_training(link,
> +									    link_setting,
> +									    skip_video_pattern);
> +			else
> +				status = dc_link_dp_perform_link_training(link,
> +									  &current_setting,
> +									  skip_video_pattern);
> +
>  			if (status == LINK_TRAINING_SUCCESS)
>  				return true;
>  		}
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
> index 616a48d72afa..f86d4446f347 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
> @@ -366,11 +366,44 @@ void dcn31_link_encoder_construct_minimal(
>  		SIGNAL_TYPE_EDP;
>  }
>  
> +/* DPIA equivalent of link_transmitter_control. */
> +static bool link_dpia_control(struct dc_context *dc_ctx,
> +	struct dmub_cmd_dig_dpia_control_data *dpia_control)
> +{
> +	union dmub_rb_cmd cmd;
> +	struct dc_dmub_srv *dmub = dc_ctx->dmub_srv;
> +
> +	memset(&cmd, 0, sizeof(cmd));
> +
> +	cmd.dig1_dpia_control.header.type = DMUB_CMD__DPIA;
> +	cmd.dig1_dpia_control.header.sub_type =
> +			DMUB_CMD__DPIA_DIG1_DPIA_CONTROL;
> +	cmd.dig1_dpia_control.header.payload_bytes =
> +		sizeof(cmd.dig1_dpia_control) -
> +		sizeof(cmd.dig1_dpia_control.header);
> +
> +	cmd.dig1_dpia_control.dpia_control = *dpia_control;
> +
> +	dc_dmub_srv_cmd_queue(dmub, &cmd);
> +	dc_dmub_srv_cmd_execute(dmub);
> +	dc_dmub_srv_wait_idle(dmub);
> +
> +	return false;
> +}
> +
> +static void link_encoder_disable(struct dcn10_link_encoder *enc10)
> +{
> +	/* reset training complete */
> +	REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
> +}
> +
>  void dcn31_link_encoder_enable_dp_output(
>  	struct link_encoder *enc,
>  	const struct dc_link_settings *link_settings,
>  	enum clock_source_id clock_source)
>  {
> +	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
> +
>  	/* Enable transmitter and encoder. */
>  	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
>  
> @@ -378,7 +411,30 @@ void dcn31_link_encoder_enable_dp_output(
>  
>  	} else {
>  
> -		/** @todo Handle transmitter with programmable mapping to link encoder. */
> +		struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 };
> +		struct dc_link *link;
> +
> +		link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);
> +
> +		enc1_configure_encoder(enc10, link_settings);
> +
> +		dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE;
> +		dpia_control.enc_id = enc->preferred_engine;
> +		dpia_control.mode_laneset.digmode = 0; /* 0 for SST; 5 for MST */
> +		dpia_control.lanenum = (uint8_t)link_settings->lane_count;
> +		dpia_control.symclk_10khz = link_settings->link_rate *
> +				LINK_RATE_REF_FREQ_IN_KHZ / 10;
> +		dpia_control.hpdsel = 5; /* Unused by DPIA */
> +
> +		if (link) {
> +			dpia_control.dpia_id = link->ddc_hw_inst;
> +		} else {
> +			DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
> +			BREAK_TO_DEBUGGER();
> +			return;
> +		}
> +
> +		link_dpia_control(enc->ctx, &dpia_control);
>  	}
>  }
>  
> @@ -387,6 +443,8 @@ void dcn31_link_encoder_enable_dp_mst_output(
>  	const struct dc_link_settings *link_settings,
>  	enum clock_source_id clock_source)
>  {
> +	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
> +
>  	/* Enable transmitter and encoder. */
>  	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
>  
> @@ -394,7 +452,30 @@ void dcn31_link_encoder_enable_dp_mst_output(
>  
>  	} else {
>  
> -		/** @todo Handle transmitter with programmable mapping to link encoder. */
> +		struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 };
> +		struct dc_link *link;
> +
> +		link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);
> +
> +		enc1_configure_encoder(enc10, link_settings);
> +
> +		dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE;
> +		dpia_control.enc_id = enc->preferred_engine;
> +		dpia_control.mode_laneset.digmode = 5; /* 0 for SST; 5 for MST */
> +		dpia_control.lanenum = (uint8_t)link_settings->lane_count;
> +		dpia_control.symclk_10khz = link_settings->link_rate *
> +				LINK_RATE_REF_FREQ_IN_KHZ / 10;
> +		dpia_control.hpdsel = 5; /* Unused by DPIA */
> +
> +		if (link) {
> +			dpia_control.dpia_id = link->ddc_hw_inst;
> +		} else {
> +			DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
> +			BREAK_TO_DEBUGGER();
> +			return;
> +		}
> +
> +		link_dpia_control(enc->ctx, &dpia_control);
>  	}
>  }
>  
> @@ -402,6 +483,8 @@ void dcn31_link_encoder_disable_output(
>  	struct link_encoder *enc,
>  	enum signal_type signal)
>  {
> +	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
> +
>  	/* Disable transmitter and encoder. */
>  	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
>  
> @@ -409,7 +492,36 @@ void dcn31_link_encoder_disable_output(
>  
>  	} else {
>  
> -		/** @todo Handle transmitter with programmable mapping to link encoder. */
> +		struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 };
> +		struct dc_link *link;
> +
> +		if (!dcn10_is_dig_enabled(enc))
> +			return;
> +
> +		link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);
> +
> +		dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_DISABLE;
> +		dpia_control.enc_id = enc->preferred_engine;
> +		if (signal == SIGNAL_TYPE_DISPLAY_PORT) {
> +			dpia_control.mode_laneset.digmode = 0; /* 0 for SST; 5 for MST */
> +		} else if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
> +			dpia_control.mode_laneset.digmode = 5; /* 0 for SST; 5 for MST */
> +		} else {
> +			DC_LOG_ERROR("%s: USB4 DPIA only supports DisplayPort.\n", __func__);
> +			BREAK_TO_DEBUGGER();
> +		}
> +
> +		if (link) {
> +			dpia_control.dpia_id = link->ddc_hw_inst;
> +		} else {
> +			DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
> +			BREAK_TO_DEBUGGER();
> +			return;
> +		}
> +
> +		link_dpia_control(enc->ctx, &dpia_control);
> +
> +		link_encoder_disable(enc10);
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> index a693b743f0d4..8461442b03a9 100644
> --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> @@ -654,6 +654,10 @@ enum dmub_cmd_type {
>  	 * Command type used for all panel control commands.
>  	 */
>  	DMUB_CMD__PANEL_CNTL = 74,
> +	/**
> +	 * Command type used for interfacing with DPIA.
> +	 */
> +	DMUB_CMD__DPIA = 77,
>  	/**
>  	 * Command type used for EDID CEA parsing
>  	 */
> @@ -682,6 +686,11 @@ enum dmub_out_cmd_type {
>  	DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
>  };
>  
> +/* DMUB_CMD__DPIA command sub-types. */
> +enum dmub_cmd_dpia_type {
> +	DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
> +};
> +
>  #pragma pack(push, 1)
>  
>  /**
> @@ -1001,6 +1010,34 @@ struct dmub_rb_cmd_dig1_transmitter_control {
>  	union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
>  };
>  
> +/**
> + * DPIA tunnel command parameters.
> + */
> +struct dmub_cmd_dig_dpia_control_data {
> +	uint8_t enc_id;         /** 0 = ENGINE_ID_DIGA, ... */
> +	uint8_t action;         /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
> +	union {
> +		uint8_t digmode;    /** enum atom_encode_mode_def */
> +		uint8_t dplaneset;  /** DP voltage swing and pre-emphasis value */
> +	} mode_laneset;
> +	uint8_t lanenum;        /** Lane number 1, 2, 4, 8 */
> +	uint32_t symclk_10khz;  /** Symbol Clock in 10Khz */
> +	uint8_t hpdsel;         /** =0: HPD is not assigned */
> +	uint8_t digfe_sel;      /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
> +	uint8_t dpia_id;        /** Index of DPIA */
> +	uint8_t fec_rdy : 1;
> +	uint8_t reserved : 7;
> +	uint32_t reserved1;
> +};
> +
> +/**
> + * DMUB command for DPIA tunnel control.
> + */
> +struct dmub_rb_cmd_dig1_dpia_control {
> +	struct dmub_cmd_header header;
> +	struct dmub_cmd_dig_dpia_control_data dpia_control;
> +};
> +
>  /**
>   * struct dmub_rb_cmd_dpphy_init - DPPHY init.
>   */
> @@ -2442,6 +2479,10 @@ union dmub_rb_cmd {
>  	 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
>  	 */
>  	struct dmub_rb_cmd_lvtma_control lvtma_control;
> +	/**
> +	 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
> +	 */
> +	struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
>  	/**
>  	 * Definition of a DMUB_CMD__EDID_CEA command.
>  	 */
> 




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