[AMD Official Use Only]
Have to drop this patch as the following errors were observed with it.
[ 87.420822] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying to reset the VCPU!!!
[ 88.443029] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying to reset the VCPU!!!
[ 89.465386] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying to reset the VCPU!!!
[ 90.487629] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying to reset the VCPU!!!
[ 91.510380] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying to reset the VCPU!!!
[ 92.533782] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying to reset the VCPU!!!
[ 93.557400] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying to reset the VCPU!!!
[ 94.580708] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying to reset the VCPU!!!
[ 95.603832] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying to reset the VCPU!!!
[ 96.627727] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying to reset the VCPU!!!
[ 96.657453] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, giving up!!!
[ 96.665892] [drm:amdgpu_device_ip_set_powergating_state [amdgpu]] *ERROR* set_powergating_state of IP block <uvd_v6_0> failed -1
[ 97.697422] amdgpu 0000:02:00.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on uvd (-110).
[ 98.721432] amdgpu 0000:02:00.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on uvd_enc0 (-110).
[ 99.745407] amdgpu 0000:02:00.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on uvd_enc1 (-110).
[ 99.857784] [drm:amdgpu_device_delayed_init_work_handler [amdgpu]] *ERROR* ib ring test failed (-110).
BR
Evan
> -----Original Message-----
> From: Quan, Evan <Evan.Quan@xxxxxxx>
> Sent: Monday, August 23, 2021 12:18 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Chen, Guchun
> <Guchun.Chen@xxxxxxx>; Lazar, Lijo <Lijo.Lazar@xxxxxxx>; Zhu, James
> <James.Zhu@xxxxxxx>; Liu, Leo <Leo.Liu@xxxxxxx>; Quan, Evan
> <Evan.Quan@xxxxxxx>
> Subject: [PATCH 1/4] drm/amdgpu: correct clock/power gating sequence on
> UVD/VCE suspend/resume
>
> The clocks should be gated before power. And reverse sequence should be
> used on ungating.
>
> Change-Id: Iab09f1f616560ff1083b75e95bfc6433d05d7f98
> Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 8 +++----
> drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 8 +++----
> .../powerplay/hwmgr/smu7_clockpowergating.c | 24 +++++++++----------
> .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c | 24 +++++++++-------
> ---
> 4 files changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> index 445480b50f48..859840ac5f0b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> @@ -1238,10 +1238,10 @@ static void
> amdgpu_uvd_idle_work_handler(struct work_struct *work)
> } else {
> amdgpu_asic_set_uvd_clocks(adev, 0, 0);
> /* shutdown the UVD block */
> - amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
> -
> AMD_PG_STATE_GATE);
> amdgpu_device_ip_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
>
> AMD_CG_STATE_GATE);
> + amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
> +
> AMD_PG_STATE_GATE);
> }
> } else {
> schedule_delayed_work(&adev->uvd.idle_work,
> UVD_IDLE_TIMEOUT); @@ -1262,10 +1262,10 @@ void
> amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
> amdgpu_dpm_enable_uvd(adev, true);
> } else {
> amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
> - amdgpu_device_ip_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
> -
> AMD_CG_STATE_UNGATE);
> amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
>
> AMD_PG_STATE_UNGATE);
> + amdgpu_device_ip_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
> +
> AMD_CG_STATE_UNGATE);
> }
> }
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> index 7ad83da613ed..21b4fc48d33f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> @@ -344,10 +344,10 @@ static void amdgpu_vce_idle_work_handler(struct
> work_struct *work)
> amdgpu_dpm_enable_vce(adev, false);
> } else {
> amdgpu_asic_set_vce_clocks(adev, 0, 0);
> - amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_VCE,
> -
> AMD_PG_STATE_GATE);
> amdgpu_device_ip_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_VCE,
>
> AMD_CG_STATE_GATE);
> + amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_VCE,
> +
> AMD_PG_STATE_GATE);
> }
> } else {
> schedule_delayed_work(&adev->vce.idle_work,
> VCE_IDLE_TIMEOUT); @@ -376,10 +376,10 @@ void
> amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
> amdgpu_dpm_enable_vce(adev, true);
> } else {
> amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
> - amdgpu_device_ip_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_VCE,
> -
> AMD_CG_STATE_UNGATE);
> amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_VCE,
>
> AMD_PG_STATE_UNGATE);
> + amdgpu_device_ip_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_VCE,
> +
> AMD_CG_STATE_UNGATE);
>
> }
> }
> diff --git
> a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
> index f2bda3bcbbde..e1f85f777eac 100644
> ---
> a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
> +++
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
> @@ -118,22 +118,22 @@ void smu7_powergate_uvd(struct pp_hwmgr
> *hwmgr, bool bgate)
> data->uvd_power_gated = bgate;
>
> if (bgate) {
> - amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_UVD,
> - AMD_PG_STATE_GATE);
> amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> AMD_IP_BLOCK_TYPE_UVD,
> AMD_CG_STATE_GATE);
> + amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> + AMD_IP_BLOCK_TYPE_UVD,
> + AMD_PG_STATE_GATE);
> smu7_update_uvd_dpm(hwmgr, true);
> smu7_powerdown_uvd(hwmgr);
> } else {
> smu7_powerup_uvd(hwmgr);
> - amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_UVD,
> - AMD_CG_STATE_UNGATE);
> amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> AMD_IP_BLOCK_TYPE_UVD,
> AMD_PG_STATE_UNGATE);
> + amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> + AMD_IP_BLOCK_TYPE_UVD,
> + AMD_CG_STATE_UNGATE);
> smu7_update_uvd_dpm(hwmgr, false);
> }
>
> @@ -146,22 +146,22 @@ void smu7_powergate_vce(struct pp_hwmgr
> *hwmgr, bool bgate)
> data->vce_power_gated = bgate;
>
> if (bgate) {
> - amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_VCE,
> - AMD_PG_STATE_GATE);
> amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> AMD_IP_BLOCK_TYPE_VCE,
> AMD_CG_STATE_GATE);
> + amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> + AMD_IP_BLOCK_TYPE_VCE,
> + AMD_PG_STATE_GATE);
> smu7_update_vce_dpm(hwmgr, true);
> smu7_powerdown_vce(hwmgr);
> } else {
> smu7_powerup_vce(hwmgr);
> - amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_VCE,
> - AMD_CG_STATE_UNGATE);
> amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> AMD_IP_BLOCK_TYPE_VCE,
> AMD_PG_STATE_UNGATE);
> + amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> + AMD_IP_BLOCK_TYPE_VCE,
> + AMD_CG_STATE_UNGATE);
> smu7_update_vce_dpm(hwmgr, false);
> }
> }
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
> index b94a77e4e714..a6147db548ca 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
> @@ -1957,22 +1957,22 @@ static void smu8_dpm_powergate_uvd(struct
> pp_hwmgr *hwmgr, bool bgate)
> data->uvd_power_gated = bgate;
>
> if (bgate) {
> - amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_UVD,
> - AMD_PG_STATE_GATE);
> amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> AMD_IP_BLOCK_TYPE_UVD,
> AMD_CG_STATE_GATE);
> + amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> + AMD_IP_BLOCK_TYPE_UVD,
> + AMD_PG_STATE_GATE);
> smu8_dpm_update_uvd_dpm(hwmgr, true);
> smu8_dpm_powerdown_uvd(hwmgr);
> } else {
> smu8_dpm_powerup_uvd(hwmgr);
> - amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_UVD,
> - AMD_CG_STATE_UNGATE);
> amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> AMD_IP_BLOCK_TYPE_UVD,
> AMD_PG_STATE_UNGATE);
> + amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> + AMD_IP_BLOCK_TYPE_UVD,
> + AMD_CG_STATE_UNGATE);
> smu8_dpm_update_uvd_dpm(hwmgr, false);
> }
>
> @@ -1983,24 +1983,24 @@ static void smu8_dpm_powergate_vce(struct
> pp_hwmgr *hwmgr, bool bgate)
> struct smu8_hwmgr *data = hwmgr->backend;
>
> if (bgate) {
> - amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_VCE,
> - AMD_PG_STATE_GATE);
> amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> AMD_IP_BLOCK_TYPE_VCE,
> AMD_CG_STATE_GATE);
> + amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> + AMD_IP_BLOCK_TYPE_VCE,
> + AMD_PG_STATE_GATE);
> smu8_enable_disable_vce_dpm(hwmgr, false);
> smu8_dpm_powerdown_vce(hwmgr);
> data->vce_power_gated = true;
> } else {
> smu8_dpm_powerup_vce(hwmgr);
> data->vce_power_gated = false;
> - amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_VCE,
> - AMD_CG_STATE_UNGATE);
> amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> AMD_IP_BLOCK_TYPE_VCE,
> AMD_PG_STATE_UNGATE);
> + amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> + AMD_IP_BLOCK_TYPE_VCE,
> + AMD_CG_STATE_UNGATE);
> smu8_dpm_update_vce_dpm(hwmgr);
> smu8_enable_disable_vce_dpm(hwmgr, true);
> }
> --
> 2.29.0
