It's SI. Alex On Fri, Aug 20, 2021 at 4:08 AM Sharma, Shashank <Shashank.Sharma@xxxxxxx> wrote: > > [AMD Official Use Only] > > No problem, let me dig for this information. > > Regards > Shashank > -----Original Message----- > From: Koenig, Christian <Christian.Koenig@xxxxxxx> > Sent: Friday, August 20, 2021 1:36 PM > To: Sharma, Shashank <Shashank.Sharma@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx> > Subject: Re: [PATCH v2] drm/amdgpu/OLAND: clip the ref divider max value > > Uff, I think that was SI but could be CIK as well. > > We have a table for this somewhere, but I don't have it at hand. > > Regards, > Christian. > > Am 20.08.21 um 09:43 schrieb Sharma, Shashank: > > [AMD Official Use Only] > > > > Agree, on the similar note, which Gen is OLAND BTW 😊 ? > > > > Regards > > Shashank > > -----Original Message----- > > From: Koenig, Christian <Christian.Koenig@xxxxxxx> > > Sent: Friday, August 20, 2021 12:08 PM > > To: Sharma, Shashank <Shashank.Sharma@xxxxxxx>; > > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > > Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx> > > Subject: Re: [PATCH v2] drm/amdgpu/OLAND: clip the ref divider max > > value > > > > Sounds like a good idea to me, but I would limit this generally or at least for the whole generation and not just one particular chipset. > > > > Regards, > > Christian. > > > > Am 20.08.21 um 08:05 schrieb Sharma, Shashank: > >> From 4841e5ba60e33ff798bde6cb69fbd7e137b6db9c Mon Sep 17 00:00:00 > >> 2001 > >> From: Shashank Sharma <shashank.sharma@xxxxxxx> > >> Date: Fri, 20 Aug 2021 10:20:02 +0530 > >> Subject: [PATCH v2] drm/amdgpu/OLAND: clip the ref divider max value > >> MIME-Version: 1.0 > >> Content-Type: text/plain; charset=UTF-8 > >> Content-Transfer-Encoding: 8bit > >> > >> This patch limits the ref_div_max value to 100, during the > >> calculation of PLL feedback reference divider. With current value > >> (128), the produced fb_ref_div value generates unstable output at > >> particular frequencies. Radeon driver limits this value at 100. > >> > >> On Oland, when we try to setup mode 2048x1280@60 (a bit weird, I > >> know), it demands a clock of 221270 Khz. It's been observed that the > >> PLL calculations using values 128 and 100 are vastly different, and > >> look like this: > >> > >> +------------------------------------------+ > >> |Parameter |AMDGPU |Radeon | > >> | | | | > >> +-------------+----------------------------+ > >> |Clock feedback | | divider max | 128 > >> || 100 | cap value | | | > >> | | | | > >> | | | | > >> +------------------------------------------+ > >> |ref_div_max | | | > >> | | 42 | 20 | > >> | | | | > >> | | | | > >> +------------------------------------------+ > >> |ref_div | 42 | 20 | > >> | | | | > >> +------------------------------------------+ > >> |fb_div | 10326 | 8195 | > >> +------------------------------------------+ > >> |fb_div | 1024 | 163 | > >> +------------------------------------------+ > >> |fb_dev_p | 4 | 9 | frac fb_de^_p| > >> || | > >> +----------------------------+-------------+ > >> > >> With ref_div_max value clipped at 100, AMDGPU driver can also drive > >> videmode 2048x1280@60 (221Mhz) and produce proper output without any > >> blanking and distortion on the screen. > >> > >> PS: This value was changed from 128 to 100 in Radeon driver also, here: > >> https://github.com/freedesktop/drm-tip/commit/4b21ce1b4b5d262e7d4656b > >> 8 > >> ececc891fc3cb806 > >> > >> > >> V1: > >> Got acks from: > >> Acked-by: Alex Deucher <alexander.deucher@xxxxxxx> > >> Acked-by: Christian König <christian.koenig@xxxxxxx> > >> > >> V2: > >> - Restricting the changes only for OLAND, just to avoid any > >> regression > >> for other cards. > >> - Changed unsigned -> unsigned int to make checkpatch quiet. > >> > >> Cc: Alex Deucher <Alexander.Deucher@xxxxxxx> > >> Cc: Christian König <christian.koenig@xxxxxxx> > >> Cc: Eddy Qin <Eddy.Qin@xxxxxxx> > >> Signed-off-by: Shashank Sharma <shashank.sharma@xxxxxxx> > >> --- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c | 20 > >> +++++++++++++------- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h | 3 ++- > >> drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 2 +- > >> 3 files changed, 16 insertions(+), 9 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c > >> index f2e20666c9c1..6d04c1d25bfb 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c > >> @@ -80,12 +80,17 @@ static void amdgpu_pll_reduce_ratio(unsigned > >> *nom, unsigned *den, > >> * Calculate feedback and reference divider for a given post divider. > >> Makes > >> * sure we stay within the limits. > >> */ > >> -static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, > >> unsigned post_div, > >> - unsigned fb_div_max, unsigned ref_div_max, > >> - unsigned *fb_div, unsigned *ref_div) > >> +static void amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, > >> unsigned int nom, > >> + unsigned int den, unsigned int post_div, > >> + unsigned int fb_div_max, unsigned int > >> +ref_div_max, > >> + unsigned int *fb_div, unsigned int *ref_div) > >> { > >> + > >> /* limit reference * post divider to a maximum */ > >> - ref_div_max = min(128 / post_div, ref_div_max); > >> + if (adev->asic_type == CHIP_OLAND) > >> + ref_div_max = min(100 / post_div, ref_div_max); > >> + else > >> + ref_div_max = min(128 / post_div, ref_div_max); > >> > >> /* get matching reference and feedback divider */ > >> *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), > >> ref_div_max); @@ -112,7 +117,8 @@ static void > >> amdgpu_pll_get_fb_ref_div(unsigned > >> nom, unsigned den, unsigned post_ > >> * Try to calculate the PLL parameters to generate the given frequency: > >> * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) > >> */ > >> -void amdgpu_pll_compute(struct amdgpu_pll *pll, > >> +void amdgpu_pll_compute(struct amdgpu_device *adev, > >> + struct amdgpu_pll *pll, > >> u32 freq, > >> u32 *dot_clock_p, > >> u32 *fb_div_p, > >> @@ -199,7 +205,7 @@ void amdgpu_pll_compute(struct amdgpu_pll *pll, > >> > >> for (post_div = post_div_min; post_div <= post_div_max; > >> ++post_div) { > >> unsigned diff; > >> - amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, > >> + amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, > >> +fb_div_max, > >> ref_div_max, &fb_div, &ref_div); > >> diff = abs(target_clock - (pll->reference_freq * fb_div) / > >> (ref_div * post_div)); > >> @@ -214,7 +220,7 @@ void amdgpu_pll_compute(struct amdgpu_pll *pll, > >> post_div = post_div_best; > >> > >> /* get the feedback and reference divider for the optimal value > >> */ > >> - amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, > >> ref_div_max, > >> + amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, fb_div_max, > >> ref_div_max, > >> &fb_div, &ref_div); > >> > >> /* reduce the numbers to a simpler ratio once more */ diff > >> --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h > >> index db6136f68b82..44a583d6c9b4 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h > >> @@ -24,7 +24,8 @@ > >> #ifndef __AMDGPU_PLL_H__ > >> #define __AMDGPU_PLL_H__ > >> > >> -void amdgpu_pll_compute(struct amdgpu_pll *pll, > >> +void amdgpu_pll_compute(struct amdgpu_device *adev, > >> + struct amdgpu_pll *pll, > >> u32 freq, > >> u32 *dot_clock_p, > >> u32 *fb_div_p, > >> diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c > >> b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c > >> index 159a2a4385a1..afad094f84c2 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c > >> @@ -851,7 +851,7 @@ void amdgpu_atombios_crtc_set_pll(struct drm_crtc > >> *crtc, struct drm_display_mode > >> pll->reference_div = amdgpu_crtc->pll_reference_div; > >> pll->post_div = amdgpu_crtc->pll_post_div; > >> > >> - amdgpu_pll_compute(pll, amdgpu_crtc->adjusted_clock, &pll_clock, > >> + amdgpu_pll_compute(adev, pll, amdgpu_crtc->adjusted_clock, > >> &pll_clock, > >> &fb_div, &frac_fb_div, &ref_div, &post_div); > >> > >> amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, > >> amdgpu_crtc->pll_id,
