[AMD Official Use Only]
ping
> -----Original Message-----
> From: Peng Ju Zhou <PengJu.Zhou@xxxxxxx>
> Sent: Monday, August 9, 2021 5:37 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Zhao, Jiange <Jiange.Zhao@xxxxxxx>; Zhou, Peng Ju
> <PengJu.Zhou@xxxxxxx>
> Subject: [PATCH] drm/amdgpu: Add MB_REQ_MSG_READY_TO_RESET
> response when VF get FLR notification.
>
> From: Jiange Zhao <Jiange.Zhao@xxxxxxx>
>
> When guest received FLR notification from host, it would lock adapter into
> reset state. There will be no more job submission and hardware access after
> that.
>
> Then it should send a response to host that it has prepared for host reset.
>
> Signed-off-by: Jiange Zhao <Jiange.Zhao@xxxxxxx>
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h | 3 ++-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
> b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
> index b48e68f46a5c..a35e6d87e537 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
> @@ -287,6 +287,8 @@ static void xgpu_nv_mailbox_flr_work(struct
> work_struct *work)
> amdgpu_virt_fini_data_exchange(adev);
> atomic_set(&adev->in_gpu_reset, 1);
>
> + xgpu_nv_mailbox_trans_msg(adev, IDH_READY_TO_RESET, 0, 0, 0);
> +
> do {
> if (xgpu_nv_mailbox_peek_msg(adev) ==
> IDH_FLR_NOTIFICATION_CMPL)
> goto flr_done;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
> b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
> index 9f5808616174..73887b0aa1d6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
> @@ -37,7 +37,8 @@ enum idh_request {
> IDH_REQ_GPU_RESET_ACCESS,
> IDH_REQ_GPU_INIT_DATA,
>
> - IDH_LOG_VF_ERROR = 200,
> + IDH_LOG_VF_ERROR = 200,
> + IDH_READY_TO_RESET = 201,
> };
>
> enum idh_event {
> --
> 2.17.1
