On Tue, Jul 13, 2021 at 6:31 AM Peng Ju Zhou <PengJu.Zhou@xxxxxxx> wrote:
>
> The previous logic is recording the amount of valid vcn instances
> to use them on SRIOV, it is a hard task due to the vcn accessment is
> based on the index of the vcn instance.
>
> Check if the vcn instance enabled before do instance init.
>
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 33 ++++++++++++++++-----------
> 1 file changed, 20 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index c3580de3ea9c..d11fea2c9d90 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -88,9 +88,7 @@ static int vcn_v3_0_early_init(void *handle)
> int i;
>
> if (amdgpu_sriov_vf(adev)) {
> - for (i = 0; i < VCN_INSTANCES_SIENNA_CICHLID; i++)
> - if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i))
> - adev->vcn.num_vcn_inst++;
> + adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
> adev->vcn.harvest_config = 0;
> adev->vcn.num_enc_rings = 1;
>
> @@ -151,8 +149,7 @@ static int vcn_v3_0_sw_init(void *handle)
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
>
> - if ((adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) ||
> - (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)) {
> + if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) {
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
> adev->firmware.fw_size +=
> @@ -322,18 +319,28 @@ static int vcn_v3_0_hw_init(void *handle)
> continue;
>
> ring = &adev->vcn.inst[i].ring_dec;
> - ring->wptr = 0;
> - ring->wptr_old = 0;
> - vcn_v3_0_dec_ring_set_wptr(ring);
> - ring->sched.ready = true;
> -
> - for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
> - ring = &adev->vcn.inst[i].ring_enc[j];
> + if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) {
> + ring->sched.ready = false;
> + dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
> + } else {
> ring->wptr = 0;
> ring->wptr_old = 0;
> - vcn_v3_0_enc_ring_set_wptr(ring);
> + vcn_v3_0_dec_ring_set_wptr(ring);
> ring->sched.ready = true;
> }
> +
> + for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
> + ring = &adev->vcn.inst[i].ring_enc[j];
> + if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
> + ring->sched.ready = false;
> + dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
> + } else {
> + ring->wptr = 0;
> + ring->wptr_old = 0;
> + vcn_v3_0_enc_ring_set_wptr(ring);
> + ring->sched.ready = true;
> + }
> + }
> }
> } else {
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> --
> 2.17.1
>
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