On 2021-06-30 10:07 a.m., Nicholas Kazlauskas wrote:
> [Why & How]
> Extend existing support for DCN2.1 DMUB diagnostic logging to
> DCN3.1 so we can collect useful information if the DMUB hangs.
>
> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@xxxxxxx>
Reviewed-by: Harry Wentland <harry.wentland@xxxxxxx>
Harry
> ---
> .../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 60 +++++++++++++++++++
> .../gpu/drm/amd/display/dmub/src/dmub_dcn31.h | 16 ++++-
> .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 5 +-
> 3 files changed, 76 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
> index 8c886ece71..973de34641 100644
> --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
> +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
> @@ -352,3 +352,63 @@ uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub)
> {
> return REG_READ(DMCUB_TIMER_CURRENT);
> }
> +
> +void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
> +{
> + uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
> + uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
> +
> + if (!dmub || !diag_data)
> + return;
> +
> + memset(diag_data, 0, sizeof(*diag_data));
> +
> + diag_data->dmcub_version = dmub->fw_version;
> +
> + diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
> + diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
> + diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
> + diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
> + diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
> + diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
> + diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
> + diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
> + diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
> + diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
> + diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
> + diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
> + diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
> + diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
> + diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
> + diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
> +
> + diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
> + diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
> + diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
> +
> + diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
> + diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
> + diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
> +
> + diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
> + diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
> + diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
> +
> + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
> + diag_data->is_dmcub_enabled = is_dmub_enabled;
> +
> + REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
> + diag_data->is_dmcub_soft_reset = is_soft_reset;
> +
> + REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
> + diag_data->is_dmcub_secure_reset = is_sec_reset;
> +
> + REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
> + diag_data->is_traceport_en = is_traceport_enabled;
> +
> + REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
> + diag_data->is_cw0_enabled = is_cw0_enabled;
> +
> + REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
> + diag_data->is_cw6_enabled = is_cw6_enabled;
> +}
> diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h
> index 2829c3e9a3..9456a6a2d5 100644
> --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h
> +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h
> @@ -36,6 +36,9 @@ struct dmub_srv;
> DMUB_SR(DMCUB_CNTL) \
> DMUB_SR(DMCUB_CNTL2) \
> DMUB_SR(DMCUB_SEC_CNTL) \
> + DMUB_SR(DMCUB_INBOX0_SIZE) \
> + DMUB_SR(DMCUB_INBOX0_RPTR) \
> + DMUB_SR(DMCUB_INBOX0_WPTR) \
> DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
> DMUB_SR(DMCUB_INBOX1_SIZE) \
> DMUB_SR(DMCUB_INBOX1_RPTR) \
> @@ -103,11 +106,15 @@ struct dmub_srv;
> DMUB_SR(DMCUB_SCRATCH14) \
> DMUB_SR(DMCUB_SCRATCH15) \
> DMUB_SR(DMCUB_GPINT_DATAIN1) \
> + DMUB_SR(DMCUB_GPINT_DATAOUT) \
> DMUB_SR(CC_DC_PIPE_DIS) \
> DMUB_SR(MMHUBBUB_SOFT_RESET) \
> DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
> DMUB_SR(DCN_VM_FB_OFFSET) \
> - DMUB_SR(DMCUB_TIMER_CURRENT)
> + DMUB_SR(DMCUB_TIMER_CURRENT) \
> + DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
> + DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
> + DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR)
>
> #define DMUB_DCN31_FIELDS() \
> DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
> @@ -115,6 +122,7 @@ struct dmub_srv;
> DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
> DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
> DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
> + DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
> DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
> DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
> DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
> @@ -138,11 +146,13 @@ struct dmub_srv;
> DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
> DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
> DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
> - DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET)
> + DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
> + DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR)
>
> struct dmub_srv_dcn31_reg_offset {
> #define DMUB_SR(reg) uint32_t reg;
> DMUB_DCN31_REGS()
> + DMCUB_INTERNAL_REGS()
> #undef DMUB_SR
> };
>
> @@ -227,4 +237,6 @@ void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
>
> uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub);
>
> +void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);
> +
> #endif /* _DMUB_DCN31_H_ */
> diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
> index a195734b4d..e58740afdc 100644
> --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
> +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
> @@ -211,6 +211,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
> #ifdef CONFIG_DRM_AMD_DC_DCN3_1
>
> case DMUB_ASIC_DCN31:
> + dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
> funcs->reset = dmub_dcn31_reset;
> funcs->reset_release = dmub_dcn31_reset_release;
> funcs->backdoor_load = dmub_dcn31_backdoor_load;
> @@ -234,9 +235,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
> funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;
> funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;
>
> - if (asic == DMUB_ASIC_DCN31) {
> - dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
> - }
> + funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data;
>
> funcs->get_current_time = dmub_dcn31_get_current_time;
>
>
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