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[Public] >From: Liu, Zhan <Zhan.Liu@xxxxxxx>
>Sent: Monday, June 21, 2021 9:13 PM
>To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>; Cornij, Nikola <Nikola.Cornij@xxxxxxx>
>Cc: Liu, Charlene <Charlene.Liu@xxxxxxx>
>Subject: [PATCH] drm/amd/display: Enabling eDP no power sequencing with DAL feature mask
>
>[Public]
>
>[Why]
>Sometimes, DP receiver chip power-controlled externally by an
>Embedded Controller could be treated and used as eDP,
>if it drives mobile display. In this case,
>we shouldn't be doing power-sequencing, hence we can skip
>waiting for T7-ready and T9-ready."
>
>[How]
>Added a feature mask to enable eDP no power sequencing feature.
>
>To enable this, set 0x10 flag in amdgpu.dcfeaturemask on
>Linux command line.
>
>Signed-off-by: Zhan Liu <zhan.liu@xxxxxxx>
Reviewed-by: Nikola Cornij <Nikola.Cornij@xxxxxxx>
>Change-Id: I15e8fb2979fe3ff5491ccf1ee384693d4dce787c
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++
> drivers/gpu/drm/amd/display/dc/dc.h | 1 +
> .../display/dc/dce110/dce110_hw_sequencer.c | 31 ++++++++++++++++---
> drivers/gpu/drm/amd/include/amd_shared.h | 10 +++---
> 5 files changed, 38 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>index 3de1accb060e..b588cf4398db 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>@@ -159,6 +159,7 @@ int amdgpu_smu_pptable_id = -1;
> * highest. That helps saving some idle power.
> * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
> * PSR (bit 3) disabled by default
>+ * EDP NO POWER SEQUENCING (bit 4) disabled by default
> */
> uint amdgpu_dc_feature_mask = 2;
> uint amdgpu_dc_debug_mask;
>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>index c0a3119982b0..abba26c8f20a 100644
>--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>@@ -1174,6 +1174,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
> init_data.flags.disable_fractional_pwm = true;
>
>+ if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
>+ init_data.flags.edp_no_power_sequencing = true;
>+
> init_data.flags.power_down_display_on_boot = true;
>
> INIT_LIST_HEAD(&adev->dm.da_list);
>diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
>index a70697898025..7f1d2d6f9de8 100644
>--- a/drivers/gpu/drm/amd/display/dc/dc.h
>+++ b/drivers/gpu/drm/amd/display/dc/dc.h
>@@ -297,6 +297,7 @@ struct dc_config {
> bool allow_seamless_boot_optimization;
> bool power_down_display_on_boot;
> bool edp_not_connected;
>+ bool edp_no_power_sequencing;
> bool force_enum_edp;
> bool forced_clocks;
> bool allow_lttpr_non_transparent_mode;
>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
>index 53dd305fa6b0..013d94c9506a 100644
>--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
>+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
>@@ -1023,8 +1023,20 @@ void dce110_edp_backlight_control(
> /* dc_service_sleep_in_milliseconds(50); */
> /*edp 1.2*/
> panel_instance = link->panel_cntl->inst;
>- if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
>- edp_receiver_ready_T7(link);
>+
>+ if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
>+ if (!link->dc->config.edp_no_power_sequencing)
>+ /*
>+ * Sometimes, DP receiver chip power-controlled externally by an
>+ * Embedded Controller could be treated and used as eDP,
>+ * if it drives mobile display. In this case,
>+ * we shouldn't be doing power-sequencing, hence we can skip
>+ * waiting for T7-ready.
>+ */
>+ edp_receiver_ready_T7(link);
>+ else
>+ DC_LOG_DC("edp_receiver_ready_T7 skipped\n");
>+ }
>
> if (ctx->dc->ctx->dmub_srv &&
> ctx->dc->debug.dmub_command_table) {
>@@ -1049,8 +1061,19 @@ void dce110_edp_backlight_control(
> dc_link_backlight_enable_aux(link, enable);
>
> /*edp 1.2*/
>- if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
>- edp_add_delay_for_T9(link);
>+ if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {
>+ if (!link->dc->config.edp_no_power_sequencing)
>+ /*
>+ * Sometimes, DP receiver chip power-controlled externally by an
>+ * Embedded Controller could be treated and used as eDP,
>+ * if it drives mobile display. In this case,
>+ * we shouldn't be doing power-sequencing, hence we can skip
>+ * waiting for T9-ready.
>+ */
>+ edp_add_delay_for_T9(link);
>+ else
>+ DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
>+ }
>
> if (!enable && link->dpcd_sink_ext_caps.bits.oled)
> msleep(OLED_PRE_T11_DELAY);
>diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
>index 9ab706cd07ff..d326339cb3cd 100644
>--- a/drivers/gpu/drm/amd/include/amd_shared.h
>+++ b/drivers/gpu/drm/amd/include/amd_shared.h
>@@ -223,10 +223,12 @@ enum amd_harvest_ip_mask {
> };
>
> enum DC_FEATURE_MASK {
>- DC_FBC_MASK = 0x1,
>- DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
>- DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
>- DC_PSR_MASK = 0x8,
>+ //Default value can be found at "uint amdgpu_dc_feature_mask"
>+ DC_FBC_MASK = (1 << 0), //0x1, disabled by default
>+ DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), //0x2, enabled by default
>+ DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), //0x4, disabled by default
>+ DC_PSR_MASK = (1 << 3), //0x8, disabled by default
>+ DC_EDP_NO_POWER_SEQUENCING = (1 << 4), //0x10, disabled by default
> };
>
> enum DC_DEBUG_MASK {
>--
>2.25.1
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