[Public]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
AMD Ryzen 9 5900H, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
Sapphire Pulse RX5700XT with the following display types:
4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Reference AMD RX6800 with the following display types:
4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems.
Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
Thank you,
Dan Wheeler
Technologist | AMD
SW Display
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1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
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-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Bindu Ramamurthy
Sent: June 18, 2021 1:35 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Brol, Eryk <Eryk.Brol@xxxxxxx>; Li, Sun peng (Leo) <Sunpeng.Li@xxxxxxx>; Wentland, Harry <Harry.Wentland@xxxxxxx>; Zhuo, Qingqing <Qingqing.Zhuo@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Jacob, Anson <Anson.Jacob@xxxxxxx>; Pillai, Aurabindo <Aurabindo.Pillai@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; R, Bindu <Bindu.R@xxxxxxx>
Subject: [PATCH 00/12] June, 21, 2021
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* DC 3.2.141
* Firmware release 0.0.71
* Improvements across LTTPR, edp initialization, DML calculations,
VBIOS for dcn302 and dcn303 etc.
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.71
Aric Cyr (2):
drm/amd/display: Multiplane cursor position incorrect when plane
rotated
drm/amd/display: 3.2.141
This version brings along following fixes:
- FW release 0.0.71.
- get socBB from VBIOS for dcn302 and dcn303.
- refclk from MICROSECOND_TIME_BASE_DIV HW register.
- Clear lane settings after LTTPRs have been trained.
- Clamp VStartup value at DML calculations.
Aurabindo Pillai (1):
drm/amd/display: get socBB from VBIOS for dcn302 and dcn303
Charlene Liu (1):
drm/amd/display: get refclk from MICROSECOND_TIME_BASE_DIV HW register
Josip Pavic (1):
drm/amd/display: do not compare integers of different widths
Martin Tsai (1):
drm/amd/display: Clear lane settings after LTTPRs have been trained
Nikola Cornij (1):
drm/amd/display: Clamp VStartup value at DML calculations time
Roman Li (1):
drm/amd/display: Delay PSR entry
Stylon Wang (1):
drm/amd/display: Revert "Guard ASSR with internal display flag"
Wesley Chalmers (1):
drm/amd/display: Fix incorrect variable name
ollogush (1):
drm/amd/display: Fix edp_bootup_bl_level initialization issue
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h | 3 +
.../drm/amd/display/dc/bios/bios_parser2.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 66 +++++---------
.../drm/amd/display/dc/core/dc_link_dpcd.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 13 ++-
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 3 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 15 +++-
.../amd/display/dc/dcn302/dcn302_resource.c | 20 +++++
.../amd/display/dc/dcn303/dcn303_resource.c | 20 +++++
.../dc/dml/dcn31/display_mode_vba_31.c | 4 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 90 ++++++++++++++++++-
15 files changed, 197 insertions(+), 57 deletions(-)
--
2.25.1
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