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[Public]
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Anson Jacob <Anson.Jacob@xxxxxxx>
Sent: Tuesday, June 8, 2021 11:36 AM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Cc: Brol, Eryk <Eryk.Brol@xxxxxxx>; Li, Sun peng (Leo) <Sunpeng.Li@xxxxxxx>; Wentland, Harry <Harry.Wentland@xxxxxxx>; Zhuo, Qingqing <Qingqing.Zhuo@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Li, Roman <Roman.Li@xxxxxxx>; Jacob, Anson <Anson.Jacob@xxxxxxx>; Pillai, Aurabindo <Aurabindo.Pillai@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; R, Bindu <Bindu.R@xxxxxxx> Subject: [PATCH] drm/amd/display: Fix build break 1. Remove duplicate OTG_PIXEL_RATE_CNTL from dccg_registers
2. Fixes: 18827ee0cc28 ("drm/amd/display: Refactor visual confirm") Signed-off-by: Anson Jacob <Anson.Jacob@xxxxxxx> --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 1 - drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 3 +-- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index 6bdab06667c9..62904d7ca100 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -202,7 +202,6 @@ struct dccg_registers { #if defined(CONFIG_DRM_AMD_DC_DCN3_1) uint32_t PHYDSYMCLK_CLOCK_CNTL; uint32_t PHYESYMCLK_CLOCK_CNTL; - uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO; diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c index 69da1493b277..e3048f8827d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c @@ -100,6 +100,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = { .z10_restore = dcn31_z10_restore, .is_abm_supported = dcn31_is_abm_supported, .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, + .update_visual_confirm_color = dcn20_update_visual_confirm_color, }; static const struct hwseq_private_funcs dcn31_private_funcs = { @@ -129,8 +130,6 @@ static const struct hwseq_private_funcs dcn31_private_funcs = { .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, .dsc_pg_control = dcn31_dsc_pg_control, - .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color, - .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color, .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=""> |
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