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Reviewed-by: Horace Chen <horace.chen@xxxxxxx>
发件人: Koenig, Christian <Christian.Koenig@xxxxxxx>
发送时间: 2021年6月8日 3:41 收件人: Khaire, Rohit <Rohit.Khaire@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>; Kuehling, Felix <Felix.Kuehling@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Deng, Emily <Emily.Deng@xxxxxxx>; Liu, Monk <Monk.Liu@xxxxxxx>; Zhou, Peng Ju <PengJu.Zhou@xxxxxxx>; Chen, Horace <Horace.Chen@xxxxxxx> 抄送: Ming, Davis <Davis.Ming@xxxxxxx> 主题: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV Am 07.06.21 um 21:39 schrieb Rohit Khaire: > This is similar to IH_RB_CNTL programming in > navi10_ih_toggle_ring_interrupts > > Signed-off-by: Rohit Khaire <rohit.khaire@xxxxxxx> Acked-by: Christian König <christian.koenig@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 +++++++++++++++----- > 2 files changed, 17 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > index 47ceb783e2a5..058b1b1271e1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > @@ -683,6 +683,8 @@ int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, > > psp_prep_reg_prog_cmd_buf(cmd, reg, value); > ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); > + if (ret) > + DRM_ERROR("PSP failed to program reg id %d", reg); > > kfree(cmd); > return ret; > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c > index eac564e8dd52..376ea281c4a7 100644 > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c > @@ -120,11 +120,23 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev, > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, > RB_USED_INT_THRESHOLD, threshold); > > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); > + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { > + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) > + return; > + } else { > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); > + } > + > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); > ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, > RB_USED_INT_THRESHOLD, threshold); > - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); > + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { > + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl)) > + return; > + } else { > + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); > + } > + > WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); > } > > @@ -153,10 +165,8 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); > > if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { > - if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { > - DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); > + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) > return -ETIMEDOUT; > - } > } else { > WREG32(ih_regs->ih_rb_cntl, tmp); > } |
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