[AMD Official Use Only]
> -----Original Message-----
> From: Lazar, Lijo <Lijo.Lazar@xxxxxxx>
> Sent: Thursday, June 3, 2021 7:04 PM
> To: Quan, Evan <Evan.Quan@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>
> Subject: Re: [PATCH 4/5] drm/amd/pm: clear the cached dpm feature status
>
>
>
> On 6/3/2021 10:26 AM, Evan Quan wrote:
> > For some ASICs, the real dpm feature disablement job is handled by
> > PMFW during baco reset and custom pptable loading. Cached dpm feature
> > status need to be cleared to pair that.
> >
> > Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9
> > Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
> > ---
> > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 18
> ++++++++++++++++--
> > 1 file changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index c9a31556e077..fd7b1b8edeb7 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -1352,6 +1352,16 @@ static int smu_hw_init(void *handle)
> > return 0;
> > }
> >
> > +static void smu_reset_cached_dpm_feature_status(struct smu_context
> > +*smu) {
> > + struct smu_feature *feature = &smu->smu_feature;
> > +
> > + mutex_lock(&feature->mutex);
> > + bitmap_zero(feature->enabled, feature->feature_num);
> > + bitmap_zero(feature->supported, feature->feature_num);
>
> This will clear also clear the BACO feature status. Won't that affect using baco
> exit for runtime pm resume?
[Quan, Evan] Yes, you are right. Will update it.
Regards,
Evan
>
> Thanks,
> Lijo
>
> > + mutex_unlock(&feature->mutex);
> > +}
> > +
> > static int smu_disable_dpms(struct smu_context *smu)
> > {
> > struct amdgpu_device *adev = smu->adev; @@ -1374,16 +1384,20
> @@
> > static int smu_disable_dpms(struct smu_context *smu)
> > */
> > if (smu->uploading_custom_pp_table &&
> > (adev->asic_type >= CHIP_NAVI10) &&
> > - (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
> > + (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) {
> > + smu_reset_cached_dpm_feature_status(smu);
> > return 0;
> > + }
> >
> > /*
> > * For Sienna_Cichlid, PMFW will handle the features disablement
> properly
> > * on BACO in. Driver involvement is unnecessary.
> > */
> > if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
> > - use_baco)
> > + use_baco) {
> > + smu_reset_cached_dpm_feature_status(smu);
> > return 0;
> > + }
> >
> > /*
> > * For gpu reset, runpm and hibernation through BACO,
> >
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