Yes, I double checked all gfx9 ASICs with sriov supported.
-----Original Message-----
From: Liu, Shaoyun <Shaoyun.Liu@xxxxxxx>
Sent: June 3, 2021 11:11 AM
To: Luo, Zhigang <Zhigang.Luo@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Luo, Zhigang <Zhigang.Luo@xxxxxxx>
Subject: RE: [PATCH 2/5] drm/amdgpu: remove sriov vf gfxhub fb location programming
[AMD Official Use Only]
This looks will affect other ASIC , Can you double check that ?
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Zhigang Luo
Sent: Thursday, June 3, 2021 10:13 AM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Luo, Zhigang <Zhigang.Luo@xxxxxxx>
Subject: [PATCH 2/5] drm/amdgpu: remove sriov vf gfxhub fb location programming
host driver programmed the gfxhub fb location for vf, no need to program in guest side.
Signed-off-by: Zhigang Luo <zhigang.luo@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 063e48df0b2d..f51fd0688eca 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -320,18 +320,6 @@ static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
static int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) {
- if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) {
- /*
- * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
- * VF copy registers so vbios post doesn't program them, for
- * SRIOV driver need to program them
- */
- WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
- adev->gmc.vram_start >> 24);
- WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
- adev->gmc.vram_end >> 24);
- }
-
/* GART Enable. */
gfxhub_v1_0_init_gart_aperture_regs(adev);
gfxhub_v1_0_init_system_aperture_regs(adev);
--
2.17.1
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