On Tue, Jun 1, 2021 at 12:28 PM shaoyunl <shaoyun.liu@xxxxxxx> wrote: > > On SRIOV, driver should only access register through RLC in runtime > > Signed-off-by: shaoyunl <shaoyun.liu@xxxxxxx> Acked-by: Alex Deucher <alexander.deucher@xxxxxxx> > Change-Id: Iecaa52436a2985a18ede9c86cb00cc197a717bd6 > --- > drivers/gpu/drm/amd/amdgpu/soc15_common.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h > index c781808e4dc3..f6cf70e69cce 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h > +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h > @@ -28,12 +28,12 @@ > #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) > > #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \ > - ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \ > + ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \ > adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \ > WREG32(reg, value)) > > #define __RREG32_SOC15_RLC__(reg, flag, hwip) \ > - ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \ > + ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \ > adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \ > RREG32(reg)) > > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
