Re: [PATCH v5 03/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10*

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Am 2021-05-17 um 10:39 a.m. schrieb Peng Ju Zhou:
> In SRIOV environment, KMD should access GC registers
> with RLCG if GC indirect access flag enabled.
>
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@xxxxxxx>

This patch is

Reviewed-by: Felix Kuehling <Felix.Kuehling@xxxxxxx>


> ---
>  .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c    | 42 +++++++++----------
>  1 file changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> index 62aa1a6f64ed..491acdf92f73 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> @@ -96,8 +96,8 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
>  
>  	lock_srbm(kgd, 0, 0, 0, vmid);
>  
> -	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
> -	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
> +	WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
> +	WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
>  	/* APE1 no longer exists on GFX9 */
>  
>  	unlock_srbm(kgd);
> @@ -161,7 +161,7 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
>  
>  	lock_srbm(kgd, mec, pipe, 0, 0);
>  
> -	WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
> +	WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
>  		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
>  		CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
>  
> @@ -239,13 +239,13 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>  
>  	for (reg = hqd_base;
>  	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
> -		WREG32(reg, mqd_hqd[reg - hqd_base]);
> +		WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
>  
>  
>  	/* Activate doorbell logic before triggering WPTR poll. */
>  	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
>  			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
> -	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
> +	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
>  
>  	if (wptr) {
>  		/* Don't read wptr with get_user because the user
> @@ -274,27 +274,27 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>  		guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
>  		guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
>  
> -		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
> +		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
>  		       lower_32_bits(guessed_wptr));
> -		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
> +		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
>  		       upper_32_bits(guessed_wptr));
> -		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
> +		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
>  		       lower_32_bits((uint64_t)wptr));
> -		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
> +		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
>  		       upper_32_bits((uint64_t)wptr));
>  		pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
>  			 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
> -		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
> +		WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
>  		       (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
>  	}
>  
>  	/* Start the EOP fetcher */
> -	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
> +	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR,
>  	       REG_SET_FIELD(m->cp_hqd_eop_rptr,
>  			     CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
>  
>  	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
> -	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
> +	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
>  
>  	release_queue(kgd);
>  
> @@ -365,7 +365,7 @@ static int kgd_hqd_dump(struct kgd_dev *kgd,
>  		if (WARN_ON_ONCE(i >= HQD_N_REGS))	\
>  			break;				\
>  		(*dump)[i][0] = (addr) << 2;		\
> -		(*dump)[i++][1] = RREG32(addr);		\
> +		(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr);		\
>  	} while (0)
>  
>  	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
> @@ -497,13 +497,13 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
>  	uint32_t low, high;
>  
>  	acquire_queue(kgd, pipe_id, queue_id);
> -	act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
> +	act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
>  	if (act) {
>  		low = lower_32_bits(queue_address >> 8);
>  		high = upper_32_bits(queue_address >> 8);
>  
> -		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
> -		   high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
> +		if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
> +		   high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
>  			retval = true;
>  	}
>  	release_queue(kgd);
> @@ -621,11 +621,11 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
>  	preempt_enable();
>  #endif
>  
> -	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
> +	WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
>  
>  	end_jiffies = (utimeout * HZ / 1000) + jiffies;
>  	while (true) {
> -		temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
> +		temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
>  		if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
>  			break;
>  		if (time_after(jiffies, end_jiffies)) {
> @@ -716,8 +716,8 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd,
>  
>  	mutex_lock(&adev->grbm_idx_mutex);
>  
> -	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);
> -	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
> +	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
> +	WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd);
>  
>  	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
>  		INSTANCE_BROADCAST_WRITES, 1);
> @@ -726,7 +726,7 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd,
>  	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
>  		SE_BROADCAST_WRITES, 1);
>  
> -	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
> +	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
>  	mutex_unlock(&adev->grbm_idx_mutex);
>  
>  	return 0;
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx



[Index of Archives]     [Linux USB Devel]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]

  Powered by Linux