On Fri, May 14, 2021 at 3:27 AM Peng Ju Zhou <PengJu.Zhou@xxxxxxx> wrote: > > Change RLCG/SOC15 register access interface to triage > GC/MMHUB access from MMIO to RLCG. > > Signed-off-by: Peng Ju Zhou <PengJu.Zhou@xxxxxxx> I think patches 1-4, 16 need to be squashed together to avoid breaking the build. Please also provide a description of how the new macros work in the patch description. Describe how the reworked macros properly handle sending GC and MMHUB accesses via the RLC rather than via some other mechanism. It's really hard to follow the macro logic. Alex > --- > drivers/gpu/drm/amd/amdgpu/soc15_common.h | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h > index 14bd794bbea6..9b18e19f4c73 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h > +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h > @@ -27,6 +27,16 @@ > /* Register Access Macros */ > #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) > > +#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \ > + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \ > + adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \ > + WREG32(reg, value)) > + > +#define __RREG32_SOC15_RLC__(reg, flag, hwip) \ > + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \ > + adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \ > + RREG32(reg)) > + > #define WREG32_FIELD15(ip, idx, reg, field, val) \ > WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ > (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
