On Sat, Mar 20, 2021 at 04:09:47AM +0200, Ville Syrjälä wrote:
> On Fri, Mar 19, 2021 at 10:45:10PM +0100, Mario Kleiner wrote:
> > On Fri, Mar 19, 2021 at 10:16 PM Ville Syrjälä
> > <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> > >
> > > On Fri, Mar 19, 2021 at 10:03:13PM +0100, Mario Kleiner wrote:
> > > > These are 16 bits per color channel unsigned normalized formats.
> > > > They are supported by at least AMD display hw, and suitable for
> > > > direct scanout of Vulkan swapchain images in the format
> > > > VK_FORMAT_R16G16B16A16_UNORM.
> > > >
> > > > Signed-off-by: Mario Kleiner <mario.kleiner.de@xxxxxxxxx>
> > > > ---
> > > > drivers/gpu/drm/drm_fourcc.c | 4 ++++
> > > > include/uapi/drm/drm_fourcc.h | 7 +++++++
> > > > 2 files changed, 11 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> > > > index 03262472059c..ce13d2be5d7b 100644
> > > > --- a/drivers/gpu/drm/drm_fourcc.c
> > > > +++ b/drivers/gpu/drm/drm_fourcc.c
> > > > @@ -203,6 +203,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
> > > > { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> > > > { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> > > > { .format = DRM_FORMAT_AXBXGXRX106106106106, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> > > > + { .format = DRM_FORMAT_XRGB16161616, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> > > > + { .format = DRM_FORMAT_XBGR16161616, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> > > > + { .format = DRM_FORMAT_ARGB16161616, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> > > > + { .format = DRM_FORMAT_ABGR16161616, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> > > > { .format = DRM_FORMAT_RGB888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> > > > { .format = DRM_FORMAT_BGR888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> > > > { .format = DRM_FORMAT_XRGB8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > > index f76de49c768f..f7156322aba5 100644
> > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > @@ -168,6 +168,13 @@ extern "C" {
> > > > #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
> > > > #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
> > > >
> > > > +/* 64 bpp RGB */
> > > > +#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
> > > > +#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
> > > > +
> > > > +#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
> > > > +#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
> > >
> > > These look reasonable enough to me. IIRC we should be able to expose
> > > them on some recent Intel hw as well.
> > >
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > >
> >
> > Thanks Ville!
> >
> > Indeed i looked over the Intel PRM's, and while fp16 support seems to
> > be rather recent (Gen8? Gen9? Gen10? Can't remember atm.), iirc, I
> > found references to rgb16 fixed point back to gen5 / Ironlake.
>
> fp16 has been around since forever (gen4+)
> uint16 is much more recent, IIRC is something ~glk+
FYI I just hacked something together for i915:
git://github.com/vsyrjala/linux.git uint16
Tests seem to pass on a glk here at least.
--
Ville Syrjälä
Intel
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