[AMD Official Use Only - Internal Distribution Only]
Maybe the title can be more specific like:
drm/amdgpu: force enable gfx ras in hw_support for vega20 ws
With above modified.
Reviewed-by: Feifei Xu <Feifei.Xu@xxxxxxx>
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Stanley.Yang
Sent: Friday, April 30, 2021 2:52 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Zhang, Hawking <Hawking.Zhang@xxxxxxx>
Cc: Yang, Stanley <Stanley.Yang@xxxxxxx>
Subject: [PATCH Review 1/1] drm/amdgpu: force enable gfx ras for vega20 ws
Signed-off-by: Stanley.Yang <Stanley.Yang@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index daf63a4c1fff..dfeaa57dd7ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -34,6 +34,7 @@
#include "amdgpu_xgmi.h"
#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
#include <asm/mce.h>
+#include "atom.h"
static const char *RAS_FS_NAME = "ras";
@@ -2070,6 +2071,25 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
adev->asic_type == CHIP_SIENNA_CICHLID; }
+/*
+ * this is workaround for vega20 workstation sku,
+ * force enable gfx ras, ignore vbios gfx ras flag
+ * due to GC EDC can not write
+ */
+static void amdgpu_ras_get_quirks(struct amdgpu_device *adev,
+uint32_t *hw_supported)
+{
+struct atom_context *ctx = adev->mode_info.atom_context;
+
+if (!ctx)
+return;
+
+if (adev->asic_type == CHIP_VEGA20 &&
+strnstr(ctx->vbios_version, "D16406",
+sizeof(ctx->vbios_version)))
+*hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX); }
+
/*
* check hardware's ras ability which will be saved in hw_supported.
* if hardware does not support ras, we can skip some ras initializtion and @@ -2112,6 +2132,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
1 << AMDGPU_RAS_BLOCK__MMHUB);
}
+amdgpu_ras_get_quirks(adev, hw_supported);
+
/* hw_supported needs to be aligned with RAS block mask. */
*hw_supported &= AMDGPU_RAS_BLOCK_MASK;
--
2.17.1
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