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[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Tao Zhou <tao.zhou1@xxxxxxx>
From: Jiansong Chen <Jiansong.Chen@xxxxxxx>
Sent: Monday, April 19, 2021 4:47 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Cc: Zhou1, Tao <Tao.Zhou1@xxxxxxx>; Gui, Jack <Jack.Gui@xxxxxxx>; Chen, Jiansong (Simon) <Jiansong.Chen@xxxxxxx> Subject: [PATCH] drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish dimgrey_cavefish has similar gc_10_3 ip with sienna_cichlid,
so follow its registers offset setting. Signed-off-by: Jiansong Chen <Jiansong.Chen@xxxxxxx> Change-Id: I2c8f1022c0b4c5baf70d09ec99b7b2ca8da36bba --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 85a6a10e048f..49fd10a15707 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3377,7 +3377,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), -- 2.25.1 |
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