[AMD Public Use] Hi all, This week this patchset was tested on a HP Envy 360, with Ryzen 5 4500U, on the following display types (via usb-c to dp/dvi/hdmi/vga): 4k 60z, 1440p 144hz, 1680*1050 60hz, internal eDP 1080p 60hz Tested on a Sapphire Pulse RX5700XT on the following display types (via DP): 4k60 60hz, 1440p 144hz, 1680x1050 60hz. Also tested on a Reference AMD RX6800 on the following display types (via DP): 4k60 60hz, 1440p 144hz. Tested using a MST hub at 2x 4k 30hz on all systems. Tested by Dan Wheeler <daniel.wheeler@xxxxxxx> Thank you, Dan Wheeler Technologist | AMD SW Display O +(1) 905-882-2600 ext. 74665 ------------------------------------------------------------------------------------------------------------------ 1 Commerce Valley Dr E, Thornhill, ON L3T 7X6 Facebook | Twitter | amd.com -----Original Message----- From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Qingqing Zhuo Sent: April 1, 2021 12:45 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Brol, Eryk <Eryk.Brol@xxxxxxx>; Li, Sun peng (Leo) <Sunpeng.Li@xxxxxxx>; Wentland, Harry <Harry.Wentland@xxxxxxx>; Zhuo, Qingqing <Qingqing.Zhuo@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Li, Roman <Roman.Li@xxxxxxx>; Jacob, Anson <Anson.Jacob@xxxxxxx>; Pillai, Aurabindo <Aurabindo.Pillai@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; R, Bindu <Bindu.R@xxxxxxx> Subject: [PATCH 00/21] DC Patches April 5, 2021 This DC patchset brings improvements in multiple areas. In summary, we highlight: * Firmware release 0.0.59 * Fixes on display experiences for 4k TVs, register mask missing, etc. * Enhancements on MST, code cleaning and debug messages. --- Anson Jacob (1): drm/amd/display: Fix 32 bit compilation of dmub_srv.c Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.59 Aric Cyr (1): drm/amd/display: 3.2.130 Aurabindo Pillai (1): drm/amd/display: Add debugfs entry for LTTPR register status David (Dingchen) Zhang (1): drm/amd/display: use MST downstream AUX to dump DPRX CRCs Harry VanZyllDeJong (1): drm/amd/display: Fixed corruption on 4K tvs Harry Wentland (2): drm/amd/display: Add debug prints for SMU messages drm/amd/display: Add dc_debug flag to disable min fclk Jake Wang (1): drm/amd/display: Added dc_edp_id_count to dc_context Leo Li (1): drm/amd/display: Move vupdate keepout programming from DCN20 to DCN10 Mikita Lipski (4): drm/amd/display: Set initial value to a divider drm/amd/display: Directly retrain link from debugfs drm/amd/display: Add MST capability to trigger_hotplug interface drm/amd/display: Determine synchronization edge based on master's vsync Nicholas Kazlauskas (1): drm/amd/display: Cleanup DML DSC input bpc validation Qingqing Zhuo (1): drm/amd/display: Add missing mask for DCN3 Robin Singh (1): drm/amd/display: add NULL check to avoid kernel crash in DC. Victor Lu (1): drm/amd/display: Add function and debugfs to dump DCC_EN bit Wayne Lin (1): drm/amd/display: Tweak the kernel doc for crc_rd_wrk Wyatt Wood (2): drm/amd/display: Retry getting PSR state if command times out drm/amd/display: Add delay in dmub_srv_send_gpint_command .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 2 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 207 +++++++++++++++++- .../display/dc/clk_mgr/dcn301/dcn301_smu.c | 29 ++- .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 +- drivers/gpu/drm/amd/display/dc/dc.h | 3 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 4 +- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 29 ++- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 ++ .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 4 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 3 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 16 ++ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 3 + .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 + .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 16 -- .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 3 - .../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 3 +- .../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 3 +- .../drm/amd/display/dc/dcn301/dcn301_init.c | 3 +- .../amd/display/dc/dcn301/dcn301_resource.c | 2 +- .../drm/amd/display/dc/dml/display_mode_lib.c | 2 +- .../amd/display/dc/dml/display_mode_structs.h | 4 +- .../drm/amd/display/dc/dml/display_mode_vba.c | 8 +- .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 17 +- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 4 +- .../amd/display/modules/freesync/freesync.c | 4 +- 32 files changed, 364 insertions(+), 71 deletions(-) -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cdaniel.wheeler%40amd.com%7C84c9e134049d4e1f021508d8f52da0a9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637528923620041029%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=4Sg%2Byv5%2BEdqOLHP0Rulb94nfeyZBvEeIlGZb0DjzaCY%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx