[AMD Public Use] Hi all, This week this patchset was tested on a HP Envy 360, with Ryzen 5 4500U, on the following display types (via usb-c to dp/dvi/hdmi/vga): 4k 60z, 1440p 144hz, 1680*1050 60hz, internal eDP 1080p 60hz Tested on a Sapphire Pulse RX5700XT on the following display types (via DP): 4k60 60hz, 1440p 144hz, 1680x1050 60hz. Also tested on a Reference AMD RX6800 on the following display types (via DP): 4k60 60hz, 1440p 144hz. Also used a MST hub at 2x 4k 30hz on all systems. Did not see a visual impact from the patchset tested. Thank you, Dan Wheeler Technologist | AMD SW Display O +(1) 905-882-2600 ext. 74665 ------------------------------------------------------------------------------------------------------------------ 1 Commerce Valley Dr E, Thornhill, ON L3T 7X6 Facebook | Twitter | amd.com -----Original Message----- From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Solomon Chiu Sent: March 19, 2021 9:47 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Brol, Eryk <Eryk.Brol@xxxxxxx>; Chiu, Solomon <Solomon.Chiu@xxxxxxx>; Li, Sun peng (Leo) <Sunpeng.Li@xxxxxxx>; Wentland, Harry <Harry.Wentland@xxxxxxx>; Zhuo, Qingqing <Qingqing.Zhuo@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Jacob, Anson <Anson.Jacob@xxxxxxx>; Pillai, Aurabindo <Aurabindo.Pillai@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; R, Bindu <Bindu.R@xxxxxxx> Subject: [PATCH 00/14] DC Patches March 22, 2021 This DC patchset brings improvements in multiple areas. In summary, we highlight: * Populate socclk entries for dcn2.1 * hide VGH asic specific structs * Add kernel doc to crc_rd_wrk field * revert max lb lines change * Log DMCUB trace buffer events * Fix debugfs link_settings entry * revert max lb use by default for n10 * Deallocate IRQ handlers on amdgpu_dm_irq_fini * Fixed Clock Recovery Sequence * Fix UBSAN: shift-out-of-bounds warning * [FW Promotion] Release 0.0.57 * Change input parameter for set_drr * Use pwrseq instance to determine eDP instance Alvin Lee (1): drm/amd/display: Change input parameter for set_drr Anson Jacob (1): drm/amd/display: Fix UBSAN: shift-out-of-bounds warning Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.57 Aric Cyr (1): drm/amd/display: 3.2.128 David Galiffi (1): drm/amd/display: Fixed Clock Recovery Sequence Dmytro Laktyushkin (3): drm/amd/display: hide VGH asic specific structs drm/amd/display: revert max lb lines change drm/amd/display: revert max lb use by default for n10 Fangzhi Zuo (1): drm/amd/display: Fix debugfs link_settings entry Jake Wang (1): drm/amd/display: Use pwrseq instance to determine eDP instance Leo (Hanghong) Ma (1): drm/amd/display: Log DMCUB trace buffer events Roman Li (1): drm/amd/display: Populate socclk entries for dcn2.1 Victor Lu (1): drm/amd/display: Deallocate IRQ handlers on amdgpu_dm_irq_fini Wayne Lin (1): drm/amd/display: Add kernel doc to crc_rd_wrk field .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 48 ++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 14 +++ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 15 +-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 12 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 71 +++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 21 ++++ .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 116 +++++++++++++----- .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 13 ++ .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 101 +++++++-------- .../display/dc/clk_mgr/dcn301/vg_clk_mgr.h | 28 ++--- drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- .../display/dc/dce110/dce110_hw_sequencer.c | 9 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +-- .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 3 +- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 6 +- .../drm/amd/display/dc/dcn21/dcn21_resource.c | 3 +- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +- .../amd/display/dc/dcn301/dcn301_resource.c | 2 +- .../amd/display/dc/dcn302/dcn302_resource.c | 2 +- .../dc/dml/dcn20/display_rq_dlg_calc_20.c | 28 ++++- .../dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 28 ++++- .../dc/dml/dcn21/display_rq_dlg_calc_21.c | 28 ++++- .../dc/dml/dcn30/display_rq_dlg_calc_30.c | 28 ++++- .../display/dc/dml/dml1_display_rq_dlg_calc.c | 28 ++++- .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 9 -- .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 +- .../display/dc/irq/dcn21/irq_service_dcn21.c | 32 ++++- .../display/dc/irq/dcn30/irq_service_dcn30.c | 32 ++++- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +- .../amd/display/modules/freesync/freesync.c | 37 ++++-- .../amd/display/modules/inc/mod_freesync.h | 7 +- 35 files changed, 581 insertions(+), 197 deletions(-) -- 2.29.0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cdaniel.wheeler%40amd.com%7C6f07175d95c342eab41908d8eb57410f%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637518107284787999%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=XFDn1gjvchG61%2FxUrmWgzDpe22XKXWWktzfokHncJTw%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
