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[AMD Official Use Only - Internal Distribution Only]
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Evan Quan <evan.quan@xxxxxxx>
Sent: Friday, March 19, 2021 2:53 AM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Cc: Quan, Evan <Evan.Quan@xxxxxxx> Subject: [PATCH 2/2] drm/amd/pm: label these APIs used internally as static Also drop unnecessary header file and declarations.
Change-Id: I877b48c32c599534798e14e271c3e700b0d6ebf6 Signed-off-by: Evan Quan <evan.quan@xxxxxxx> --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 1 - drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 - drivers/gpu/drm/amd/amdgpu/nv.c | 1 - drivers/gpu/drm/amd/amdgpu/soc15.c | 1 - drivers/gpu/drm/amd/pm/amdgpu_pm.c | 10 +- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 61 +-------- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 159 +++++++++++++--------- 7 files changed, 98 insertions(+), 136 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 33f748e5bbfc..1429c6897d3f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -24,7 +24,6 @@ #include <linux/list.h> #include "amdgpu.h" #include "amdgpu_xgmi.h" -#include "amdgpu_smu.h" #include "amdgpu_ras.h" #include "soc15.h" #include "df/df_3_6_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index d780b9c0926f..9a65ff871a58 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -29,7 +29,6 @@ #include "amdgpu.h" #include "amdgpu_gfx.h" #include "amdgpu_psp.h" -#include "amdgpu_smu.h" #include "nv.h" #include "nvd.h" diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index a31ef68ee2ab..e9cc3201054f 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -34,7 +34,6 @@ #include "amdgpu_vce.h" #include "amdgpu_ucode.h" #include "amdgpu_psp.h" -#include "amdgpu_smu.h" #include "atom.h" #include "amd_pcie.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 3808402cd964..c354a11e2fd9 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -76,7 +76,6 @@ #include "smuio_v13_0.h" #include "dce_virtual.h" #include "mxgpu_ai.h" -#include "amdgpu_smu.h" #include "amdgpu_ras.h" #include "amdgpu_xgmi.h" #include <uapi/linux/kfd_ioctl.h> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 74fa5fe89970..10c761b11ff7 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -27,7 +27,6 @@ #include "amdgpu_drv.h" #include "amdgpu_pm.h" #include "amdgpu_dpm.h" -#include "amdgpu_smu.h" #include "atom.h" #include <linux/pci.h> #include <linux/hwmon.h> @@ -930,14 +929,7 @@ static ssize_t amdgpu_set_pp_features(struct device *dev, return ret; } - if (is_support_sw_smu(adev)) { - ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask); - if (ret) { - pm_runtime_mark_last_busy(ddev->dev); - pm_runtime_put_autosuspend(ddev->dev); - return -EINVAL; - } - } else if (adev->powerplay.pp_funcs->set_ppfeature_status) { + if (adev->powerplay.pp_funcs->set_ppfeature_status) { ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); if (ret) { pm_runtime_mark_last_busy(ddev->dev); diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h index ca5a0a436cad..517f333fbc4b 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h @@ -1281,50 +1281,22 @@ int smu_load_microcode(struct smu_context *smu); int smu_check_fw_status(struct smu_context *smu); -int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); - -int smu_set_fan_speed_rpm(void *handle, uint32_t speed); - int smu_get_power_limit(struct smu_context *smu, uint32_t *limit, enum smu_ppt_limit_level limit_level); -int smu_set_power_limit(void *handle, uint32_t limit); -int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf); - -int smu_od_edit_dpm_table(void *handle, - enum PP_OD_DPM_TABLE_COMMAND type, - long *input, uint32_t size); - -int smu_read_sensor(void *handle, int sensor, void *data, int *size); -int smu_get_power_profile_mode(void *handle, char *buf); -int smu_set_power_profile_mode(void *handle, long *param, uint32_t param_size); -u32 smu_get_fan_control_mode(void *handle); -int smu_set_fan_control_mode(struct smu_context *smu, int value); -void smu_pp_set_fan_control_mode(void *handle, u32 value); -int smu_get_fan_speed_percent(void *handle, u32 *speed); -int smu_set_fan_speed_percent(void *handle, u32 speed); -int smu_get_fan_speed_rpm(void *handle, uint32_t *speed); - -int smu_set_xgmi_pstate(void *handle, - uint32_t pstate); - int smu_set_azalia_d3_pme(struct smu_context *smu); bool smu_baco_is_support(struct smu_context *smu); -int smu_get_baco_capability(void *handle, bool *cap); int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state); int smu_baco_enter(struct smu_context *smu); int smu_baco_exit(struct smu_context *smu); -int smu_baco_set_state(void *handle, int state); - bool smu_mode1_reset_is_support(struct smu_context *smu); bool smu_mode2_reset_is_support(struct smu_context *smu); int smu_mode1_reset(struct smu_context *smu); -int smu_mode2_reset(void *handle); extern const struct amd_ip_funcs smu_ip_funcs; @@ -1334,48 +1306,23 @@ extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; bool is_support_sw_smu(struct amdgpu_device *adev); bool is_support_cclk_dpm(struct amdgpu_device *adev); -int smu_reset(struct smu_context *smu); -int smu_sys_get_pp_table(void *handle, char **table); -int smu_sys_set_pp_table(void *handle, const char *buf, size_t size); -int smu_get_power_num_states(void *handle, struct pp_states_info *state_info); -enum amd_pm_state_type smu_get_current_power_state(void *handle); int smu_write_watermarks_table(struct smu_context *smu); /* smu to display interface */ extern int smu_dpm_set_power_gate(void *handle, uint32_t block_type, bool gate); -extern int smu_handle_task(struct smu_context *smu, - enum amd_dpm_forced_level level, - enum amd_pp_task task_id, - bool lock_needed); -extern int smu_handle_dpm_task(void *handle, - enum amd_pp_task task_id, - enum amd_pm_state_type *user_state); -int smu_switch_power_profile(void *handle, - enum PP_SMC_POWER_PROFILE type, - bool en); + int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); -u32 smu_get_mclk(void *handle, bool low); -u32 smu_get_sclk(void *handle, bool low); + int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); -enum amd_dpm_forced_level smu_get_performance_level(void *handle); -int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level); + int smu_set_ac_dc(struct smu_context *smu); -int smu_sys_get_pp_feature_mask(void *handle, char *buf); -int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask); -int smu_force_ppclk_levels(void *handle, enum pp_clock_type type, uint32_t mask); -int smu_set_mp1_state(void *handle, - enum pp_mp1_state mp1_state); -int smu_set_df_cstate(void *handle, - enum pp_df_cstate state); + int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value); -ssize_t smu_sys_get_gpu_metrics(void *handle, void **table); - -int smu_enable_mgpu_fan_boost(void *handle); int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state); int smu_set_light_sbr(struct smu_context *smu, bool enable); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index db56cb3693a3..35aa1d234535 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -51,8 +51,19 @@ static const struct amd_pm_funcs swsmu_pm_funcs; static int smu_force_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); - -int smu_sys_get_pp_feature_mask(void *handle, char *buf) +static int smu_handle_task(struct smu_context *smu, + enum amd_dpm_forced_level level, + enum amd_pp_task task_id, + bool lock_needed); +static int smu_reset(struct smu_context *smu); +static int smu_set_fan_speed_percent(void *handle, u32 speed); +static int smu_set_fan_control_mode(struct smu_context *smu, int value); +static int smu_set_power_limit(void *handle, uint32_t limit); +static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); +static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); + +static int smu_sys_get_pp_feature_mask(void *handle, + char *buf) { struct smu_context *smu = handle; int size = 0; @@ -69,7 +80,8 @@ int smu_sys_get_pp_feature_mask(void *handle, char *buf) return size; } -int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask) +static int smu_sys_set_pp_feature_mask(void *handle, + uint64_t new_mask) { struct smu_context *smu = handle; int ret = 0; @@ -142,7 +154,7 @@ int smu_get_dpm_freq_range(struct smu_context *smu, return ret; } -u32 smu_get_mclk(void *handle, bool low) +static u32 smu_get_mclk(void *handle, bool low) { struct smu_context *smu = handle; uint32_t clk_freq; @@ -156,7 +168,7 @@ u32 smu_get_mclk(void *handle, bool low) return clk_freq * 100; } -u32 smu_get_sclk(void *handle, bool low) +static u32 smu_get_sclk(void *handle, bool low) { struct smu_context *smu = handle; uint32_t clk_freq; @@ -256,7 +268,8 @@ static int smu_dpm_set_jpeg_enable(struct smu_context *smu, * Under this case, the smu->mutex lock protection is already enforced on * the parent API smu_force_performance_level of the call path. */ -int smu_dpm_set_power_gate(void *handle, uint32_t block_type, +int smu_dpm_set_power_gate(void *handle, + uint32_t block_type, bool gate) { struct smu_context *smu = handle; @@ -412,8 +425,8 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu) smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; } -int smu_get_power_num_states(void *handle, - struct pp_states_info *state_info) +static int smu_get_power_num_states(void *handle, + struct pp_states_info *state_info) { if (!state_info) return -EINVAL; @@ -448,7 +461,8 @@ bool is_support_cclk_dpm(struct amdgpu_device *adev) } -int smu_sys_get_pp_table(void *handle, char **table) +static int smu_sys_get_pp_table(void *handle, + char **table) { struct smu_context *smu = handle; struct smu_table_context *smu_table = &smu->smu_table; @@ -474,7 +488,9 @@ int smu_sys_get_pp_table(void *handle, char **table) return powerplay_table_size; } -int smu_sys_set_pp_table(void *handle, const char *buf, size_t size) +static int smu_sys_set_pp_table(void *handle, + const char *buf, + size_t size) { struct smu_context *smu = handle; struct smu_table_context *smu_table = &smu->smu_table; @@ -638,6 +654,7 @@ static int smu_set_default_dpm_table(struct smu_context *smu) return ret; } + static int smu_late_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1538,8 +1555,8 @@ static int smu_resume(void *handle) return 0; } -int smu_display_configuration_change(void *handle, - const struct amd_pp_display_configuration *display_config) +static int smu_display_configuration_change(void *handle, + const struct amd_pp_display_configuration *display_config) { struct smu_context *smu = handle; int index = 0; @@ -1732,9 +1749,9 @@ int smu_handle_task(struct smu_context *smu, return ret; } -int smu_handle_dpm_task(void *handle, - enum amd_pp_task task_id, - enum amd_pm_state_type *user_state) +static int smu_handle_dpm_task(void *handle, + enum amd_pp_task task_id, + enum amd_pm_state_type *user_state) { struct smu_context *smu = handle; struct smu_dpm_context *smu_dpm = &smu->smu_dpm; @@ -1743,10 +1760,9 @@ int smu_handle_dpm_task(void *handle, } - -int smu_switch_power_profile(void *handle, - enum PP_SMC_POWER_PROFILE type, - bool en) +static int smu_switch_power_profile(void *handle, + enum PP_SMC_POWER_PROFILE type, + bool en) { struct smu_context *smu = handle; struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); @@ -1782,7 +1798,7 @@ int smu_switch_power_profile(void *handle, return 0; } -enum amd_dpm_forced_level smu_get_performance_level(void *handle) +static enum amd_dpm_forced_level smu_get_performance_level(void *handle) { struct smu_context *smu = handle; struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); @@ -1801,7 +1817,8 @@ enum amd_dpm_forced_level smu_get_performance_level(void *handle) return level; } -int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level) +static int smu_force_performance_level(void *handle, + enum amd_dpm_forced_level level) { struct smu_context *smu = handle; struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); @@ -1836,7 +1853,7 @@ int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level) return ret; } -int smu_set_display_count(void *handle, uint32_t count) +static int smu_set_display_count(void *handle, uint32_t count) { struct smu_context *smu = handle; int ret = 0; @@ -1881,7 +1898,9 @@ static int smu_force_smuclk_levels(struct smu_context *smu, return ret; } -int smu_force_ppclk_levels(void *handle, enum pp_clock_type type, uint32_t mask) +static int smu_force_ppclk_levels(void *handle, + enum pp_clock_type type, + uint32_t mask) { struct smu_context *smu = handle; enum smu_clk_type clk_type; @@ -1925,8 +1944,8 @@ int smu_force_ppclk_levels(void *handle, enum pp_clock_type type, uint32_t mask) * However, the mp1 state setting should still be granted * even if the dpm_enabled cleared. */ -int smu_set_mp1_state(void *handle, - enum pp_mp1_state mp1_state) +static int smu_set_mp1_state(void *handle, + enum pp_mp1_state mp1_state) { struct smu_context *smu = handle; int ret = 0; @@ -1945,8 +1964,8 @@ int smu_set_mp1_state(void *handle, return ret; } -int smu_set_df_cstate(void *handle, - enum pp_df_cstate state) +static int smu_set_df_cstate(void *handle, + enum pp_df_cstate state) { struct smu_context *smu = handle; int ret = 0; @@ -2005,8 +2024,8 @@ int smu_write_watermarks_table(struct smu_context *smu) return ret; } -int smu_set_watermarks_for_clock_ranges(void *handle, - struct pp_smu_wm_range_sets *clock_ranges) +static int smu_set_watermarks_for_clock_ranges(void *handle, + struct pp_smu_wm_range_sets *clock_ranges) { struct smu_context *smu = handle; int ret = 0; @@ -2143,7 +2162,7 @@ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) return ret; } -int smu_set_fan_speed_rpm(void *handle, uint32_t speed) +static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) { struct smu_context *smu = handle; int ret = 0; @@ -2202,7 +2221,7 @@ int smu_get_power_limit(struct smu_context *smu, return ret; } -int smu_set_power_limit(void *handle, uint32_t limit) +static int smu_set_power_limit(void *handle, uint32_t limit) { struct smu_context *smu = handle; uint32_t limit_type = limit >> 24; @@ -2258,7 +2277,9 @@ static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type cl return ret; } -int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf) +static int smu_print_ppclk_levels(void *handle, + enum pp_clock_type type, + char *buf) { struct smu_context *smu = handle; enum smu_clk_type clk_type; @@ -2299,9 +2320,9 @@ int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf) return smu_print_smuclk_levels(smu, clk_type, buf); } -int smu_od_edit_dpm_table(void *handle, - enum PP_OD_DPM_TABLE_COMMAND type, - long *input, uint32_t size) +static int smu_od_edit_dpm_table(void *handle, + enum PP_OD_DPM_TABLE_COMMAND type, + long *input, uint32_t size) { struct smu_context *smu = handle; int ret = 0; @@ -2320,7 +2341,10 @@ int smu_od_edit_dpm_table(void *handle, return ret; } -int smu_read_sensor(void *handle, int sensor, void *data, int *size_arg) +static int smu_read_sensor(void *handle, + int sensor, + void *data, + int *size_arg) { struct smu_context *smu = handle; struct smu_umd_pstate_table *pstate_table = @@ -2387,7 +2411,7 @@ int smu_read_sensor(void *handle, int sensor, void *data, int *size_arg) return ret; } -int smu_get_power_profile_mode(void *handle, char *buf) +static int smu_get_power_profile_mode(void *handle, char *buf) { struct smu_context *smu = handle; int ret = 0; @@ -2405,7 +2429,9 @@ int smu_get_power_profile_mode(void *handle, char *buf) return ret; } -int smu_set_power_profile_mode(void *handle, long *param, uint32_t param_size) +static int smu_set_power_profile_mode(void *handle, + long *param, + uint32_t param_size) { struct smu_context *smu = handle; int ret = 0; @@ -2423,7 +2449,7 @@ int smu_set_power_profile_mode(void *handle, long *param, uint32_t param_size) } -u32 smu_get_fan_control_mode(void *handle) +static u32 smu_get_fan_control_mode(void *handle) { struct smu_context *smu = handle; u32 ret = 0; @@ -2469,14 +2495,15 @@ int smu_set_fan_control_mode(struct smu_context *smu, int value) return ret; } -void smu_pp_set_fan_control_mode(void *handle, u32 value) { +static void smu_pp_set_fan_control_mode(void *handle, u32 value) +{ struct smu_context *smu = handle; smu_set_fan_control_mode(smu, value); } -int smu_get_fan_speed_percent(void *handle, u32 *speed) +static int smu_get_fan_speed_percent(void *handle, u32 *speed) { struct smu_context *smu = handle; int ret = 0; @@ -2494,7 +2521,7 @@ int smu_get_fan_speed_percent(void *handle, u32 *speed) return ret; } -int smu_set_fan_speed_percent(void *handle, u32 speed) +static int smu_set_fan_speed_percent(void *handle, u32 speed) { struct smu_context *smu = handle; int ret = 0; @@ -2517,7 +2544,7 @@ int smu_set_fan_speed_percent(void *handle, u32 speed) return ret; } -int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) +static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) { struct smu_context *smu = handle; int ret = 0; @@ -2535,7 +2562,7 @@ int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) return ret; } -int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) +static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) { struct smu_context *smu = handle; int ret = 0; @@ -2552,9 +2579,9 @@ int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) return ret; } -int smu_get_clock_by_type_with_latency(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks) +static int smu_get_clock_by_type_with_latency(void *handle, + enum amd_pp_clock_type type, + struct pp_clock_levels_with_latency *clocks) { struct smu_context *smu = handle; enum smu_clk_type clk_type; @@ -2593,8 +2620,8 @@ int smu_get_clock_by_type_with_latency(void *handle, return ret; } -int smu_display_clock_voltage_request(void *handle, - struct pp_display_clock_request *clock_req) +static int smu_display_clock_voltage_request(void *handle, + struct pp_display_clock_request *clock_req) { struct smu_context *smu = handle; int ret = 0; @@ -2613,8 +2640,8 @@ int smu_display_clock_voltage_request(void *handle, } -int smu_display_disable_memory_clock_switch(void *handle, - bool disable_memory_clock_switch) +static int smu_display_disable_memory_clock_switch(void *handle, + bool disable_memory_clock_switch) { struct smu_context *smu = handle; int ret = -EINVAL; @@ -2632,8 +2659,8 @@ int smu_display_disable_memory_clock_switch(void *handle, return ret; } -int smu_set_xgmi_pstate(void *handle, - uint32_t pstate) +static int smu_set_xgmi_pstate(void *handle, + uint32_t pstate) { struct smu_context *smu = handle; int ret = 0; @@ -2696,7 +2723,7 @@ bool smu_baco_is_support(struct smu_context *smu) return ret; } -int smu_get_baco_capability(void *handle, bool *cap) +static int smu_get_baco_capability(void *handle, bool *cap) { struct smu_context *smu = handle; int ret = 0; @@ -2769,7 +2796,7 @@ int smu_baco_exit(struct smu_context *smu) return ret; } -int smu_baco_set_state(void *handle, int state) +static int smu_baco_set_state(void *handle, int state) { struct smu_context *smu = handle; int ret = 0; @@ -2854,7 +2881,7 @@ int smu_mode1_reset(struct smu_context *smu) return ret; } -int smu_mode2_reset(void *handle) +static int smu_mode2_reset(void *handle) { struct smu_context *smu = handle; int ret = 0; @@ -2875,8 +2902,8 @@ int smu_mode2_reset(void *handle) return ret; } -int smu_get_max_sustainable_clocks_by_dc(void *handle, - struct pp_smu_nv_clock_table *max_clocks) +static int smu_get_max_sustainable_clocks_by_dc(void *handle, + struct pp_smu_nv_clock_table *max_clocks) { struct smu_context *smu = handle; int ret = 0; @@ -2894,9 +2921,9 @@ int smu_get_max_sustainable_clocks_by_dc(void *handle, return ret; } -int smu_get_uclk_dpm_states(void *handle, - unsigned int *clock_values_in_khz, - unsigned int *num_states) +static int smu_get_uclk_dpm_states(void *handle, + unsigned int *clock_values_in_khz, + unsigned int *num_states) { struct smu_context *smu = handle; int ret = 0; @@ -2914,7 +2941,7 @@ int smu_get_uclk_dpm_states(void *handle, return ret; } -enum amd_pm_state_type smu_get_current_power_state(void *handle) +static enum amd_pm_state_type smu_get_current_power_state(void *handle) { struct smu_context *smu = handle; enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; @@ -2932,8 +2959,8 @@ enum amd_pm_state_type smu_get_current_power_state(void *handle) return pm_state; } -int smu_get_dpm_clock_table(void *handle, - struct dpm_clocks *clock_table) +static int smu_get_dpm_clock_table(void *handle, + struct dpm_clocks *clock_table) { struct smu_context *smu = handle; int ret = 0; @@ -2951,7 +2978,7 @@ int smu_get_dpm_clock_table(void *handle, return ret; } -ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) +static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) { struct smu_context *smu = handle; ssize_t size; @@ -2971,7 +2998,7 @@ ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) return size; } -int smu_enable_mgpu_fan_boost(void *handle) +static int smu_enable_mgpu_fan_boost(void *handle) { struct smu_context *smu = handle; int ret = 0; -- 2.29.0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=""> |
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