Re: [PATCH] drm/amd/display: Add irq register entry for dmub

[Harry Wentland <harry.wentland@xxxxxxx>]

On 2021-03-17 12:21 p.m., Rodrigo Siqueira wrote:
> DCN2.1 and DCN3.0 are missing some macros that register irq entries
> which cause compilation errors. This commit introduces those macros and
> fix the compilation error.
>
> Cc: Wayne Lin <Wayne.Lin@xxxxxxx>
> Cc: Solomon Chiu <solomon.chiu@xxxxxxx>
> Fixes: 53e9c0f651421136 ("drm/amd/display: Support vertical interrupt 0 for all dcn ASIC")
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@xxxxxxx>

Reviewed-by: Harry Wentland <harry.wentland@xxxxxxx>

Harry

> ---
>   .../display/dc/irq/dcn21/irq_service_dcn21.c   | 17 +++++++++++++++++
>   .../display/dc/irq/dcn30/irq_service_dcn30.c   | 18 ++++++++++++++++++
>   2 files changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
> index 48a3c360174e..bc1249a9858c 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
> @@ -209,6 +209,23 @@ static const struct irq_source_info_funcs vline0_irq_info_funcs = {
>   	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
>   			mm ## block ## id ## _ ## reg_name
>   
> +#define SRI_DMUB(reg_name)\
> +	BASE(mm ## reg_name ## _BASE_IDX) + \
> +			mm ## reg_name
> +
> +#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
> +	.enable_reg = SRI_DMUB(reg1),\
> +	.enable_mask = \
> +		reg1 ## __ ## mask1 ## _MASK,\
> +	.enable_value = {\
> +		reg1 ## __ ## mask1 ## _MASK,\
> +		~reg1 ## __ ## mask1 ## _MASK \
> +	},\
> +	.ack_reg = SRI_DMUB(reg2),\
> +	.ack_mask = \
> +		reg2 ## __ ## mask2 ## _MASK,\
> +	.ack_value = \
> +		reg2 ## __ ## mask2 ## _MASK \
>   
>   #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
>   	.enable_reg = SRI(reg1, block, reg_num),\
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
> index 68f8f554c925..5af52ad49d7c 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
> @@ -276,6 +276,24 @@ static const struct irq_source_info_funcs vline0_irq_info_funcs = {
>   		.funcs = &vblank_irq_info_funcs\
>   	}
>   
> +#define SRI_DMUB(reg_name)\
> +	BASE(mm ## reg_name ## _BASE_IDX) + \
> +			mm ## reg_name
> +
> +#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
> +	.enable_reg = SRI_DMUB(reg1),\
> +	.enable_mask = \
> +		reg1 ## __ ## mask1 ## _MASK,\
> +	.enable_value = {\
> +		reg1 ## __ ## mask1 ## _MASK,\
> +		~reg1 ## __ ## mask1 ## _MASK \
> +	},\
> +	.ack_reg = SRI_DMUB(reg2),\
> +	.ack_mask = \
> +		reg2 ## __ ## mask2 ## _MASK,\
> +	.ack_value = \
> +		reg2 ## __ ## mask2 ## _MASK \
> +
>   #define dmub_trace_int_entry()\
>   	[DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\
>   		IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\

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