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[AMD Official Use Only - Internal Distribution Only]
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Hawking Zhang <Hawking.Zhang@xxxxxxx>
Sent: Thursday, March 11, 2021 10:53 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Cc: Zhang, Hawking <Hawking.Zhang@xxxxxxx> Subject: [PATCH 2/2] drm/amdgpu: support query ecc cap for SIENNA_CICHLID driver needs to query umc_info_v3_3 for ecc capability
in sienna_cichlid Signed-off-by: Hawking Zhang <Hawking.Zhang@xxxxxxx> Reviewed-by: Likun Gao <Likun.Gao@xxxxxxx> --- .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 28 +++++++++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 +-- 2 files changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c index fd1d2cface2e..0612300284fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c @@ -117,6 +117,8 @@ union igp_info { union umc_info { struct atom_umc_info_v3_1 v31; + struct atom_umc_info_v3_2 v32; + struct atom_umc_info_v3_3 v33; }; union vram_info { @@ -343,13 +345,29 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev) if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, &frev, &crev, &data_offset)) { - /* support umc_info 3.1+ */ - if ((frev == 3 && crev >= 1) || (frev > 3)) { + if (frev == 3) { umc_info = (union umc_info *) (mode_info->atom_context->bios + data_offset); - ecc_default_enabled = - (le32_to_cpu(umc_info->v31.umc_config) & - UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; + switch (crev) { + case 1: + ecc_default_enabled = + (le32_to_cpu(umc_info->v31.umc_config) & + UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; + break; + case 2: + ecc_default_enabled = + (le32_to_cpu(umc_info->v32.umc_config) & + UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false; + break; + case 3: + ecc_default_enabled = + (le32_to_cpu(umc_info->v33.umc_config1) & + UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false; + break; + default: + /* unsupported crev */ + return false; + } } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 93699ea4860c..ce025aa4e332 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1915,11 +1915,11 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev, return; if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { - dev_info(adev->dev, "HBM ECC is active.\n"); + dev_info(adev->dev, "MEM ECC is active.\n"); *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC | 1 << AMDGPU_RAS_BLOCK__DF); } else - dev_info(adev->dev, "HBM ECC is not presented.\n"); + dev_info(adev->dev, "MEM ECC is not presented.\n"); if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { dev_info(adev->dev, "SRAM ECC is active.\n"); -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=""> |
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