[AMD Public Use] + } else { + return -EOPNOTSUPP; + } + break; The 'break' looks useless, as no chance arriving here. Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Alex Deucher Sent: Wednesday, March 10, 2021 12:12 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx> Subject: [PATCH] drm/amdgpu/powerplay/smu10: add support for gpu busy query Was added in newer versions of the firmware. Add support for it. Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx> --- drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h | 1 + .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 30 ++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h index 4c7e08ba5fa4..171f12b82716 100644 --- a/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h @@ -84,6 +84,7 @@ #define PPSMC_MSG_PowerGateMmHub 0x35 #define PPSMC_MSG_SetRccPfcPmeRestoreRegister 0x36 #define PPSMC_MSG_GpuChangeState 0x37 +#define PPSMC_MSG_GetGfxBusy 0x3D #define PPSMC_Message_Count 0x42 typedef uint16_t PPSMC_Result; diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c index c932b632ddd4..52fcdec738e9 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c @@ -1261,9 +1261,21 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, void *value, int *size) { struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - uint32_t sclk, mclk; + struct amdgpu_device *adev = hwmgr->adev; + uint32_t sclk, mclk, activity_percent; + bool has_gfx_busy; int ret = 0; + /* GetGfxBusy support was added on RV SMU FW 30.85.00 and PCO 4.30.59 */ + if ((adev->apu_flags & AMD_APU_IS_PICASSO) && + (hwmgr->smu_version >= 0x41e3b)) + has_gfx_busy = true; + else if ((adev->apu_flags & AMD_APU_IS_RAVEN) && + (hwmgr->smu_version >= 0x1e5500)) + has_gfx_busy = true; + else + has_gfx_busy = false; + switch (idx) { case AMDGPU_PP_SENSOR_GFX_SCLK: smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk); @@ -1284,6 +1296,22 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1; *size = 4; break; + case AMDGPU_PP_SENSOR_GPU_LOAD: + if (has_gfx_busy) { + ret = smum_send_msg_to_smc(hwmgr, + PPSMC_MSG_GetGfxBusy, + &activity_percent); + if (!ret) { + activity_percent = activity_percent > 100 ? 100 : activity_percent; + } else { + activity_percent = 50; + } + *((uint32_t *)value) = activity_percent; + return 0; + } else { + return -EOPNOTSUPP; + } + break; default: ret = -EOPNOTSUPP; break; -- 2.29.2 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cguchun.chen%40amd.com%7C4ae33de1e1cb46155eef08d8e37aaf58%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637509463372230606%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=MuROLcwbCeFRI8RWtgPSnrz5J4CEfG6R8yvbk8mqy%2Bg%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx