On Tue, Mar 09, 2021 at 12:45:44PM +0800, Liang, Prike wrote:
>
>
> > -----Original Message-----
> > From: Alex Deucher <alexdeucher@xxxxxxxxx>
> > Sent: Tuesday, March 9, 2021 12:07 PM
> > To: Liang, Prike <Prike.Liang@xxxxxxx>
> > Cc: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>; Deucher, Alexander
> > <Alexander.Deucher@xxxxxxx>; Huang, Ray <Ray.Huang@xxxxxxx>
> > Subject: Re: [PATCH] drm/amdgpu: fix the hibernation suspend with s0ix
> >
> > On Mon, Mar 8, 2021 at 10:52 PM Prike Liang <Prike.Liang@xxxxxxx> wrote:
> > >
> > > During system hibernation suspend still need un-gate gfx CG/PG firstly
> > > to handle HW status check before HW resource destory.
> > >
> > > Signed-off-by: Prike Liang <Prike.Liang@xxxxxxx>
> >
> > This is fine for stable, but we should work on cleaning this up. I have a patch
> > set to improve this, but it's more invasive. We really need to sort out what
> > specific parts of
> > amdgpu_device_ip_suspend_phase2() are problematic and special case
> > them. We shouldn't just be skipping that function.
> [Prike] Yeah in this stage we're just try make the s0ix been functional and stable. The AMDGPU work mode is aligning with windows KMD s0ix sequence and only suspend the DCE and IH for s0i3 entry . Will try figure out the each GNB IP idle off dependency and then improve the AMDGPU suspend/resume sequence for system-wide Sx entry/exit.
>
Maybe we need a comment before amdgpu_device_ip_suspend_phase2() to mark it
as TODO. For this moment, it's ok for me as well.
Acked-by: Huang Rui <ray.huang@xxxxxxx>
> > Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> >
> > Alex
> >
> >
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > > index e247c3a..7079bfc 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > > @@ -2683,7 +2683,7 @@ static int
> > > amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) {
> > > int i, r;
> > >
> > > - if (adev->in_poweroff_reboot_com ||
> > > + if (adev->in_poweroff_reboot_com || adev->in_hibernate ||
> > > !amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev))
> > {
> > > amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
> > > amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
> > > @@ -3750,7 +3750,7 @@ int amdgpu_device_suspend(struct drm_device
> > > *dev, bool fbcon)
> > >
> > > amdgpu_fence_driver_suspend(adev);
> > >
> > > - if (adev->in_poweroff_reboot_com ||
> > > + if (adev->in_poweroff_reboot_com || adev->in_hibernate ||
> > > !amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev))
> > > r = amdgpu_device_ip_suspend_phase2(adev);
> > > else
> > > --
> > > 2.7.4
> > >
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