[AMD Official Use Only - Internal Distribution Only]
Modified the coding style error. And resend. Thanks.
Thanks,
Feifei
-----Original Message-----
From: Feifei Xu <Feifei.Xu@xxxxxxx>
Sent: Thursday, March 4, 2021 12:54 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; alexdeucher@xxxxxxxxx
Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Xu, Feifei <Feifei.Xu@xxxxxxx>
Subject: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
SDMA 4_x asics share the same MGCG/MGLS setting.
Signed-off-by: Feifei Xu <Feifei.Xu@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..0280e8f589d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
-switch (adev->asic_type) {
-case CHIP_VEGA10:
-case CHIP_VEGA12:
-case CHIP_VEGA20:
-case CHIP_RAVEN:
-case CHIP_ARCTURUS:
-case CHIP_RENOIR:
-case CHIP_ALDEBARAN:
+if (adev->asic_type >= CHIP_VEGA10) {
sdma_v4_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
sdma_v4_0_update_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE);
-break;
-default:
-break;
}
return 0;
}
--
2.25.1
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