[AMD Official Use Only - Internal Distribution Only]
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Arunpravin
Sent: Tuesday, March 2, 2021 2:51 AM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Lazar, Lijo <Lijo.Lazar@xxxxxxx>; Paneer Selvam, Arunpravin <Arunpravin.PaneerSelvam@xxxxxxx>
Subject: [PATCH] drm/amd/pm/swsmu: clean up user profile function
Remove unnecessary comments, enable restore mode using
'|=' operator, fixes the alignment to improve the code
readability.
Signed-off-by: Arunpravin <Arunpravin.PaneerSelvam@xxxxxxx>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 22 ++++++----------------
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index f5d9590f2178..7d7ef4fa2887 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -315,35 +315,25 @@ static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_
if (smu->adev->in_suspend)
return;
- /*
- * mclk, fclk and socclk are interdependent
- * on each other
- */
if (clk == SMU_MCLK) {
- /* reset clock dependency */
smu->user_dpm_profile.clk_dependency = 0;
- /* set mclk dependent clocks(fclk and socclk) */
smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
} else if (clk == SMU_FCLK) {
- /* give priority to mclk, if mclk dependent clocks are set */
+ /* MCLK takes precedence over FCLK */
if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
return;
- /* reset clock dependency */
smu->user_dpm_profile.clk_dependency = 0;
- /* set fclk dependent clocks(mclk and socclk) */
smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
} else if (clk == SMU_SOCCLK) {
- /* give priority to mclk, if mclk dependent clocks are set */
+ /* MCLK takes precedence over SOCCLK */
if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
return;
- /* reset clock dependency */
smu->user_dpm_profile.clk_dependency = 0;
- /* set socclk dependent clocks(mclk and fclk) */
smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
} else
- /* add clk dependencies here, if any */
+ /* Add clk dependencies here, if any */
return;
}
@@ -367,7 +357,7 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu)
return;
/* Enable restore flag */
- smu->user_dpm_profile.flags = SMU_DPM_USER_PROFILE_RESTORE;
+ smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
[Quan, Evan] You may need to change other checks(e.g. "smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE ")
to use "&"( smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE) to pair with this.
Evan
/* set the user dpm power limit */
if (smu->user_dpm_profile.power_limit) {
@@ -390,8 +380,8 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu)
ret = smu_force_smuclk_levels(smu, clk_type,
smu->user_dpm_profile.clk_mask[clk_type]);
if (ret)
- dev_err(smu->adev->dev, "Failed to set clock type = %d\n",
- clk_type);
+ dev_err(smu->adev->dev,
+ "Failed to set clock type = %d\n", clk_type);
}
}
}
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cevan.quan%40amd.com%7Cd5866f2c3da84366c72108d8dce28c7e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637502212874693914%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=%2Bwe2XHK3BiX8VpVv9Ut7rJ28NJxUtWaCXo4wVpngxoM%3D&reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
