By using the information provided by PMFW when available.
V2: put those structures shared around SMU V11 ASICs in
smu_v11_0.h
Change-Id: I1afec4cd07ac9608861ee07c449e320e3f36a932
Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 10 ++++++++--
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 12 ++++-------
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 20 +++++++++++++++----
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 10 ++--------
4 files changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 50dd1529b994..d400f75e9202 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -58,6 +58,12 @@
#define CTF_OFFSET_HOTSPOT 5
#define CTF_OFFSET_MEM 5
+#define LINK_WIDTH_MAX 6
+#define LINK_SPEED_MAX 3
+
+static __maybe_unused uint8_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
+static __maybe_unused uint8_t link_speed[] = {25, 50, 80, 160};
+
static const
struct smu_temperature_range __maybe_unused smu11_thermal_policy[] =
{
@@ -284,11 +290,11 @@ int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu);
-int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
+uint8_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu);
-int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
+uint8_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
bool enablement);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index ffd37b8a3882..f71723c345a8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2716,10 +2716,8 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
- gpu_metrics->pcie_link_width =
- smu_v11_0_get_current_pcie_link_width(smu);
- gpu_metrics->pcie_link_speed =
- smu_v11_0_get_current_pcie_link_speed(smu);
+ gpu_metrics->pcie_link_width = metrics.PcieWidth;
+ gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
@@ -2856,10 +2854,8 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
- gpu_metrics->pcie_link_width =
- smu_v11_0_get_current_pcie_link_width(smu);
- gpu_metrics->pcie_link_speed =
- smu_v11_0_get_current_pcie_link_speed(smu);
+ gpu_metrics->pcie_link_width = metrics.PcieWidth;
+ gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index e74299da1739..527e02b578af 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -3124,6 +3124,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
SmuMetricsExternal_t metrics_external;
SmuMetrics_t *metrics =
&(metrics_external.SmuMetrics);
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t smu_version;
int ret = 0;
ret = smu_cmn_get_metrics_table(smu,
@@ -3170,10 +3172,20 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
gpu_metrics->current_fan_speed = metrics->CurrFanSpeed;
- gpu_metrics->pcie_link_width =
- smu_v11_0_get_current_pcie_link_width(smu);
- gpu_metrics->pcie_link_speed =
- smu_v11_0_get_current_pcie_link_speed(smu);
+ ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
+ if (ret)
+ return ret;
+
+ if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu_version > 0x003A1E00) ||
+ ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu_version > 0x00410400)) {
+ gpu_metrics->pcie_link_width = metrics->PcieWidth;
+ gpu_metrics->pcie_link_speed = link_speed[metrics->PcieRate];
+ } else {
+ gpu_metrics->pcie_link_width =
+ smu_v11_0_get_current_pcie_link_width(smu);
+ gpu_metrics->pcie_link_speed =
+ smu_v11_0_get_current_pcie_link_speed(smu);
+ }
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 60ef63073ad4..7efb7af51013 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -68,9 +68,6 @@ MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
#define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
-#define LINK_WIDTH_MAX 6
-#define LINK_SPEED_MAX 3
-
#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
@@ -99,9 +96,6 @@ MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
#define mmCG_THERMAL_STATUS_ARCT 0x90
#define mmCG_THERMAL_STATUS_ARCT_BASE_IDX 0
-static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
-static int link_speed[] = {25, 50, 80, 160};
-
int smu_v11_0_init_microcode(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
@@ -2134,7 +2128,7 @@ int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
}
-int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
+uint8_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
{
uint32_t width_level;
@@ -2154,7 +2148,7 @@ int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
>> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
}
-int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
+uint8_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
{
uint32_t speed_level;
--
2.29.0
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