[PATCH] drm/amd/pm: bump Navi1x driver if version and related data structures

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New changes were involved for the SmuMetrics strucutre.

Change-Id: Ib45443db03977ccd18618bcfdfd3574ac13d50d1
Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
---
 .../drm/amd/pm/inc/smu11_driver_if_navi10.h   | 31 ++++++++----
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h        |  6 +--
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 48 +++++++++++++++++--
 3 files changed, 70 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_navi10.h b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_navi10.h
index 246d3951a78a..84d12da19c90 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_navi10.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_navi10.h
@@ -843,19 +843,23 @@ typedef struct {
   uint16_t      FanMaximumRpm;
   uint16_t      FanMinimumPwm;
   uint16_t      FanTargetTemperature; // Degree Celcius 
+  uint16_t      FanMode;
+  uint16_t      FanMaxPwm;
+  uint16_t      FanMinPwm;
+  uint16_t      FanMaxTemp; // Degree Celcius
+  uint16_t      FanMinTemp; // Degree Celcius
   uint16_t      MaxOpTemp;            // Degree Celcius
   uint16_t      FanZeroRpmEnable;
-  uint16_t      Padding;
 
-  uint32_t     MmHubPadding[8]; // SMU internal use  
+  uint32_t     MmHubPadding[6]; // SMU internal use
 
 } OverDriveTable_t; 
 
 typedef struct {
   uint16_t CurrClock[PPCLK_COUNT];
-  uint16_t AverageGfxclkFrequency;
+  uint16_t AverageGfxclkFrequencyPostDs;
   uint16_t AverageSocclkFrequency;
-  uint16_t AverageUclkFrequency  ;
+  uint16_t AverageUclkFrequencyPostDs;
   uint16_t AverageGfxActivity    ;
   uint16_t AverageUclkActivity   ;
   uint8_t  CurrSocVoltageOffset  ;
@@ -880,15 +884,21 @@ typedef struct {
   uint8_t  Padding8_2;
   uint16_t CurrFanSpeed;
 
+  uint16_t AverageGfxclkFrequencyPreDs;
+  uint16_t AverageUclkFrequencyPreDs;
+  uint8_t  PcieRate;
+  uint8_t  PcieWidth;
+  uint8_t  Padding8_3[2];
+
   // Padding - ignore
   uint32_t     MmHubPadding[8]; // SMU internal use
 } SmuMetrics_t;
 
 typedef struct {
   uint16_t CurrClock[PPCLK_COUNT];
-  uint16_t AverageGfxclkFrequency;
+  uint16_t AverageGfxclkFrequencyPostDs;
   uint16_t AverageSocclkFrequency;
-  uint16_t AverageUclkFrequency  ;
+  uint16_t AverageUclkFrequencyPostDs;
   uint16_t AverageGfxActivity    ;
   uint16_t AverageUclkActivity   ;
   uint8_t  CurrSocVoltageOffset  ;
@@ -913,11 +923,16 @@ typedef struct {
   uint8_t  Padding8_2;
   uint16_t CurrFanSpeed;
 
-  uint32_t EnergyAccumulator;
   uint16_t AverageVclkFrequency  ;
   uint16_t AverageDclkFrequency  ;
   uint16_t VcnActivityPercentage ;
-  uint16_t padding16_2;
+  uint16_t AverageGfxclkFrequencyPreDs;
+  uint16_t AverageUclkFrequencyPreDs;
+  uint8_t  PcieRate;
+  uint8_t  PcieWidth;
+
+  uint32_t Padding32_1;
+  uint64_t EnergyAccumulator;
 
   // Padding - ignore
   uint32_t     MmHubPadding[8]; // SMU internal use
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 281835f23f6d..50dd1529b994 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -27,9 +27,9 @@
 
 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
 #define SMU11_DRIVER_IF_VERSION_ARCT 0x17
-#define SMU11_DRIVER_IF_VERSION_NV10 0x36
-#define SMU11_DRIVER_IF_VERSION_NV12 0x36
-#define SMU11_DRIVER_IF_VERSION_NV14 0x36
+#define SMU11_DRIVER_IF_VERSION_NV10 0x37
+#define SMU11_DRIVER_IF_VERSION_NV12 0x38
+#define SMU11_DRIVER_IF_VERSION_NV14 0x38
 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3D
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 6ec842811cbc..29e04f33f276 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -70,6 +70,8 @@
 	FEATURE_MASK(FEATURE_DPM_LINK_BIT)	 | \
 	FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
 
+#define SMU_11_0_GFX_BUSY_THRESHOLD 15
+
 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
 	MSG_MAP(TestMessage,			PPSMC_MSG_TestMessage,			1),
 	MSG_MAP(GetSmuVersion,			PPSMC_MSG_GetSmuVersion,		1),
@@ -515,6 +517,8 @@ static int navi10_get_smu_metrics_data(struct smu_context *smu,
 	 * same offsets for the heading parts(those members used here).
 	 */
 	SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t smu_version;
 	int ret = 0;
 
 	mutex_lock(&smu->metrics_lock);
@@ -547,13 +551,30 @@ static int navi10_get_smu_metrics_data(struct smu_context *smu,
 		*value = metrics->CurrClock[PPCLK_DCEFCLK];
 		break;
 	case METRICS_AVERAGE_GFXCLK:
-		*value = metrics->AverageGfxclkFrequency;
+		ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
+		if (ret) {
+			dev_err(adev->dev, "Failed to get smu version!\n");
+			return ret;
+		}
+		/*
+		 * The PreDs is supported by:
+		 *   - Navi10 PMFW 42.60 and onwards
+		 *   - Navi12 PMFW 52.29 and onwards
+		 *   - Navi14 PMFW 53.31 and onwards
+		 */
+		if ((metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) &&
+		     (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
+		     ((adev->asic_type == CHIP_NAVI12) && smu_version > 0x00341C00) ||
+		     ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00)))
+			*value = metrics->AverageGfxclkFrequencyPreDs;
+		else
+			*value = metrics->AverageGfxclkFrequencyPostDs;
 		break;
 	case METRICS_AVERAGE_SOCCLK:
 		*value = metrics->AverageSocclkFrequency;
 		break;
 	case METRICS_AVERAGE_UCLK:
-		*value = metrics->AverageUclkFrequency;
+		*value = metrics->AverageUclkFrequencyPostDs;
 		break;
 	case METRICS_AVERAGE_GFXACTIVITY:
 		*value = metrics->AverageGfxActivity;
@@ -2298,6 +2319,7 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
 	struct amdgpu_device *adev = smu->adev;
 	SmuMetrics_NV12_t nv12_metrics = { 0 };
 	SmuMetrics_t metrics;
+	uint32_t smu_version;
 	int ret = 0;
 
 	mutex_lock(&smu->metrics_lock);
@@ -2330,9 +2352,27 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
 
 	gpu_metrics->average_socket_power = metrics.AverageSocketPower;
 
-	gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
+	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
+	if (ret) {
+		dev_err(adev->dev, "Failed to get smu version!\n");
+		return ret;
+	}
+	/*
+	 * The PreDs is supported by:
+	 *   - Navi10 PMFW 42.60 and onwards
+	 *   - Navi12 PMFW 52.29 and onwards
+	 *   - Navi14 PMFW 53.31 and onwards
+	 */
+	if ((metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) &&
+	     (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
+	     ((adev->asic_type == CHIP_NAVI12) && smu_version > 0x00341C00) ||
+	     ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00)))
+		gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
+	else
+		gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
+
 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
-	gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
+	gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
 
 	if (adev->asic_type == CHIP_NAVI12) {
 		gpu_metrics->energy_accumulator = nv12_metrics.EnergyAccumulator;
-- 
2.29.0

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