[AMD Official Use Only - Internal Distribution Only]
Hello Christian,
I just tested the patch with Xonotic + PRIME,
I confirm that its working same as previous version, for the Freesync scenario, ie:
- With this patch, display framebuffer creation is successful, flips are coming and VRR property is getting set.
Did some negative testing also,
- Without this patch, Fremebuffer creation fails, no flips, and VRR property doesn't set.
Regards
Shashank
-----Original Message-----
From: Christian König <ckoenig.leichtzumerken@xxxxxxxxx>
Sent: Monday, February 15, 2021 5:15 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Sharma, Shashank <Shashank.Sharma@xxxxxxx>
Subject: Re: [PATCH] drm/amdgpu: Set GTT_USWC flag to enable freesync v2
Hi Shashank,
can you give this patch a test round? In theory it should work, but I'm not 100% sure.
Thanks,
Christian.
Am 15.02.21 um 12:43 schrieb Christian König:
> From: Shashank Sharma <shashank.sharma@xxxxxxx>
>
> This patch sets 'AMDGPU_GEM_CREATE_CPU_GTT_USWC' as input parameter
> flag, during object creation of an imported DMA buffer.
>
> In absence of this flag:
> 1. Function amdgpu_display_supported_domains() doesn't add
> AMDGPU_GEM_DOMAIN_GTT as supported domain.
> 2. Due to which, Function amdgpu_display_user_framebuffer_create()
> refuses to create framebuffer for imported DMA buffers.
> 3. Due to which, AddFB() IOCTL fails.
> 4. Due to which, amdgpu_present_check_flip() check fails in DDX 5. Due
> to which DDX driver doesn't allow flips (goes to blitting) 6. Due to
> which setting Freesync/VRR property fails for PRIME buffers.
>
> So, this patch finally enables Freesync with PRIME buffer offloading.
>
> v2 (chk): instead of just checking the flag we copy it over if the
> exporter is an amdgpu device as well.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@xxxxxxx>
> Signed-off-by: Christian König <christian.koenig@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> index d3727f3ab277..a54a870f006c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> @@ -422,14 +422,22 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
> {
> struct dma_resv *resv = dma_buf->resv;
> struct amdgpu_device *adev = drm_to_adev(dev);
> - struct amdgpu_bo *bo;
> struct drm_gem_object *gobj;
> + struct amdgpu_bo *bo;
> + uint64_t flags = 0;
> int ret;
>
> dma_resv_lock(resv, NULL);
> +
> + if (dma_buf->ops == &amdgpu_dmabuf_ops) {
> + struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
> +
> + flags |= other->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> + }
> +
> ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_CPU,
> - 0, ttm_bo_type_sg, resv, &gobj);
> + AMDGPU_GEM_DOMAIN_CPU, flags,
> + ttm_bo_type_sg, resv, &gobj);
> if (ret)
> goto error;
>
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