Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
On Thu, Feb 4, 2021 at 11:17 AM Nirmoy <nirmodas@xxxxxxx> wrote:
>
> ping.
>
> On 2/3/21 6:11 PM, Nirmoy Das wrote:
> > To achieve the best QoS for high priority compute jobs it is
> > required to limit waves on other compute pipes as well.
> > This patch will set min value in non high priority
> > mmSPI_WCL_PIPE_PERCENT_CS[0-3] registers to minimize the
> > impact of normal/low priority compute jobs over high priority
> > compute jobs.
> >
> > v2: use adev->gfx.mec.num_pipe_per_mec instead of hardcoding 4.
> >
> > Signed-off-by: Nirmoy Das <nirmoy.das@xxxxxxx>
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 50 ++++++++++++++++++++++++++-
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 46 +++++++++++++++++++++++-
> > 2 files changed, 94 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > index bdfd29a22b3d..84d2eaa38101 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > @@ -6846,10 +6846,45 @@ static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
> > amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
> > }
> >
> > +
> > +/* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
> > +#define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f
> > +static void gfx_v8_0_emit_wave_limit_cs(struct amdgpu_ring *ring,
> > + uint32_t pipe, bool enable)
> > +{
> > + uint32_t val;
> > + uint32_t wcl_cs_reg;
> > +
> > + val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT;
> > +
> > + switch (pipe) {
> > + case 0:
> > + wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS0;
> > + break;
> > + case 1:
> > + wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS1;
> > + break;
> > + case 2:
> > + wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS2;
> > + break;
> > + case 3:
> > + wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS3;
> > + break;
> > + default:
> > + DRM_DEBUG("invalid pipe %d\n", pipe);
> > + return;
> > + }
> > +
> > + amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
> > +
> > +}
> > +
> > #define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff
> > static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
> > {
> > + struct amdgpu_device *adev = ring->adev;
> > uint32_t val;
> > + int i;
> >
> > /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
> > * number of gfx waves. Setting 5 bit will make sure gfx only gets
> > @@ -6857,6 +6892,18 @@ static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
> > */
> > val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
> > amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
> > +
> > + /* Restrict waves for normal/low priority compute queues as well
> > + * to get best QoS for high priority compute jobs.
> > + *
> > + * amdgpu controls only 1st ME(0-3 CS pipes).
> > + */
> > + for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
> > + if (i != ring->pipe)
> > + gfx_v8_0_emit_wave_limit_cs(ring, i, enable);
> > +
> > + }
> > +
> > }
> >
> > static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
> > @@ -6943,7 +6990,8 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
> > VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
> > 7 + 7 + 7 + /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
> > 7 + /* gfx_v8_0_emit_mem_sync_compute */
> > - 5, /* gfx_v8_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
> > + 5 + /* gfx_v8_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
> > + 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */
> > .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
> > .emit_ib = gfx_v8_0_ring_emit_ib_compute,
> > .emit_fence = gfx_v8_0_ring_emit_fence_compute,
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 027997e95e46..65db88bb6cbc 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -6668,10 +6668,42 @@ static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring)
> > amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
> > }
> >
> > +static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring,
> > + uint32_t pipe, bool enable)
> > +{
> > + struct amdgpu_device *adev = ring->adev;
> > + uint32_t val;
> > + uint32_t wcl_cs_reg;
> > +
> > + /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
> > + val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT;
> > +
> > + switch (pipe) {
> > + case 0:
> > + wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0);
> > + break;
> > + case 1:
> > + wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1);
> > + break;
> > + case 2:
> > + wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2);
> > + break;
> > + case 3:
> > + wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3);
> > + break;
> > + default:
> > + DRM_DEBUG("invalid pipe %d\n", pipe);
> > + return;
> > + }
> > +
> > + amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
> > +
> > +}
> > static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
> > {
> > struct amdgpu_device *adev = ring->adev;
> > uint32_t val;
> > + int i;
> >
> >
> > /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
> > @@ -6682,6 +6714,17 @@ static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
> > amdgpu_ring_emit_wreg(ring,
> > SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX),
> > val);
> > +
> > + /* Restrict waves for normal/low priority compute queues as well
> > + * to get best QoS for high priority compute jobs.
> > + *
> > + * amdgpu controls only 1st ME(0-3 CS pipes).
> > + */
> > + for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
> > + if (i != ring->pipe)
> > + gfx_v9_0_emit_wave_limit_cs(ring, i, enable);
> > +
> > + }
> > }
> >
> > static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
> > @@ -6774,7 +6817,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
> > 2 + /* gfx_v9_0_ring_emit_vm_flush */
> > 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
> > 7 + /* gfx_v9_0_emit_mem_sync */
> > - 5, /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
> > + 5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
> > + 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */
> > .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
> > .emit_ib = gfx_v9_0_ring_emit_ib_compute,
> > .emit_fence = gfx_v9_0_ring_emit_fence,
> > --
> > 2.30.0
> >
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