Series is:
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
On Tue, Feb 2, 2021 at 1:17 AM Wayne Lin <Wayne.Lin@xxxxxxx> wrote:
>
> [Why & How]
> In order to get appropriate timing for registers which
> read/write is vertical line sensitive, add new IRQ source variable.
> This interrupt is triggered by specific vertical line,
>
> Signed-off-by: Wayne Lin <Wayne.Lin@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index ece1b41a31f9..3777f18fb1d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -852,6 +852,7 @@ struct amdgpu_device {
> /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
> struct work_struct hotplug_work;
> struct amdgpu_irq_src crtc_irq;
> + struct amdgpu_irq_src vline0_irq;
> struct amdgpu_irq_src vupdate_irq;
> struct amdgpu_irq_src pageflip_irq;
> struct amdgpu_irq_src hpd_irq;
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
