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[AMD Public Use]
Thanks for the fix.
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@xxxxxxx>
Thanks,
Bhawan
From: Yu, Lang <Lang.Yu@xxxxxxx>
Sent: January 22, 2021 7:35 AM To: Chen, Guchun <Guchun.Chen@xxxxxxx>; Huang, Ray <Ray.Huang@xxxxxxx> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Subject: RE: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue [AMD Public Use]
The header <linux/math64.h> has been included by dm_services.h. The following is the sequence, dm_services.h -> dm_services_types.h -> os_types.h -> drm/drm_print.h -> linux/device.h -> linux/pm.h -> linux/timer.h -> linux/time.h -> linux/jiffies.h -> linux/math64.h Regards, Lang -----Original Message----- From: Chen, Guchun <Guchun.Chen@xxxxxxx> Sent: Friday, January 22, 2021 5:32 PM To: Huang, Ray <Ray.Huang@xxxxxxx>; Yu, Lang <Lang.Yu@xxxxxxx> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx Subject: RE: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue [AMD Public Use] Maybe it’s good to modify subject to " drm/amd/display: fix 64-bit division issue on 32-bit OS" And if header <linux/math64.h> should be included? Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Huang Rui Sent: Friday, January 22, 2021 5:04 PM To: Yu, Lang <Lang.Yu@xxxxxxx> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx Subject: Re: [PATCH] drm/amd/display: 64-bit division on 32-bit arch issue On Fri, Jan 22, 2021 at 05:00:59PM +0800, Yu, Lang wrote: > Replace "/" with div_u64 for 32-bit arch. On 32-bit arch, the use of > "/" for 64-bit division will cause build error, i.e. > "__udivdi3/__divdi3 undefined!". > > Fixes: 27755cdf83f1 > drm/amd/display: Update dcn30_apply_idle_power_optimizations() code > > Signed-off-by: Lang Yu <Lang.Yu@xxxxxxx> Acked-by: Huang Rui <ray.huang@xxxxxxx> > --- > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > index dff83c6a142a..9620fb8a27dc 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c > @@ -772,8 +772,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > cursor_cache_enable ? &cursor_attr : NULL)) { > unsigned int v_total = stream->adjust.v_total_max ? > stream->adjust.v_total_max : stream->timing.v_total; > - unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz * > - 100LL / (v_total * stream->timing.h_total); > + unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz * > + 100LL, (v_total * stream->timing.h_total)); > > /* > * one frame time in microsec: > @@ -800,8 +800,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > unsigned int denom = refresh_hz * 6528; > unsigned int stutter_period = > dc->current_state->perf_params.stutter_period_us; > > - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * > - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / > + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * > + (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), > denom) - 64LL; > > /* scale should be increased until it fits into 6 bits */ @@ > -815,8 +815,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) > } > > denom *= 2; > - tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) * > - (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) / > + tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * > + (100LL + dc->debug.mall_additional_timer_percent) + denom - > +1), > denom) - 64LL; > } > > -- > 2.25.1 > _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=""> |
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