New policy will disable direct mmio access of this register on VF Signed-off-by: Rohit Khaire <rohit.khaire@xxxxxxx> --- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index f4e4040bbd25..48933d6f1145 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -143,6 +143,7 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, { struct amdgpu_ih_regs *ih_regs; uint32_t tmp; + int r; ih_regs = &ih->ih_regs; @@ -151,7 +152,16 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, /* enable_intr field is only valid in ring0 */ if (ih == &adev->irq.ih) tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); - WREG32(ih_regs->ih_rb_cntl, tmp); + + if (amdgpu_sriov_vf(adev)) { + r = psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, tmp); + if (r) { + DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); + return r; + } + } else { + WREG32(ih_regs->ih_rb_cntl, tmp); + } if (enable) { ih->enabled = true; @@ -246,6 +256,7 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev, { struct amdgpu_ih_regs *ih_regs; uint32_t tmp; + int r; ih_regs = &ih->ih_regs; @@ -261,7 +272,16 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev, tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); } - WREG32(ih_regs->ih_rb_cntl, tmp); + + if (amdgpu_sriov_vf(adev)) { + r = psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, tmp); + if (r) { + DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); + return r; + } + } else { + WREG32(ih_regs->ih_rb_cntl, tmp); + } if (ih == &adev->irq.ih) { /* set the ih ring 0 writeback address whether it's enabled or not */ -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx