[AMD Official Use Only - Internal Distribution Only]
This patch has been Verfied on Van Gogh.
--
Best Regards
Aaron Liu
> -----Original Message-----
> From: Huang, Ray <Ray.Huang@xxxxxxx>
> Sent: Wednesday, January 20, 2021 10:06 AM
> To: Liu, Aaron <Aaron.Liu@xxxxxxx>
> Cc: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Deucher, Alexander
> <Alexander.Deucher@xxxxxxx>
> Subject: Re: [PATCH] drm/amdgpu: update mmhub mgcg&ls for
> mmhub_v2_3
>
> On Wed, Jan 20, 2021 at 09:57:32AM +0800, Liu, Aaron wrote:
> > Starting from vangogh, the ATCL2 and DAGB0 registers relative to
> > mgcg/ls has changed.
> >
> > For MGCG:
> > Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL.
> >
> > For MGLS:
> > Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL.
> > Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers.
> >
> > Signed-off-by: Aaron Liu <aaron.liu@xxxxxxx>
>
> Could you double verify it on vangogh as well?
>
> After that, patch is
>
> Acked-by: Huang Rui <ray.huang@xxxxxxx>
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 84
> > ++++++++++++++++++-------
> > 1 file changed, 61 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > index 92f02883daa3..8f2edba5bc9e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > @@ -492,12 +492,11 @@
> > mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device
> *adev, {
> > uint32_t def, data, def1, data1;
> >
> > - def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
> > + def = data = RREG32_SOC15(MMHUB, 0,
> mmMM_ATC_L2_CGTT_CLK_CTRL);
> > def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
> >
> > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
> > - data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
> > -
> > + data &=
> ~MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;
> > data1 &=
> ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
> > DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
> > DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
> @@ -506,8
> > +505,7 @@ mmhub_v2_3_update_medium_grain_clock_gating(struct
> amdgpu_device *adev,
> > DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
> >
> > } else {
> > - data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
> > -
> > + data |=
> MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;
> > data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
> > DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
> > DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
> @@ -517,7 +515,7 @@
> > mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device
> *adev,
> > }
> >
> > if (def != data)
> > - WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
> > + WREG32_SOC15(MMHUB, 0,
> mmMM_ATC_L2_CGTT_CLK_CTRL, data);
> > if (def1 != data1)
> > WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2,
> data1); } @@ -526,17
> > +524,44 @@ static void
> > mmhub_v2_3_update_medium_grain_light_sleep(struct amdgpu_device
> *adev,
> > bool enable)
> > {
> > - uint32_t def, data;
> > -
> > - def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
> > -
> > - if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
> > - data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
> > - else
> > - data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
> > + uint32_t def, data, def1, data1, def2, data2;
> > +
> > + def = data = RREG32_SOC15(MMHUB, 0,
> mmMM_ATC_L2_CGTT_CLK_CTRL);
> > + def1 = data1 = RREG32_SOC15(MMHUB, 0,
> mmDAGB0_WR_CGTT_CLK_CTRL);
> > + def2 = data2 = RREG32_SOC15(MMHUB, 0,
> mmDAGB0_RD_CGTT_CLK_CTRL);
> > +
> > + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
> > + data &=
> ~MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;
> > + data1
> &= !(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
> > + data2 &= !(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
> |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
> > + } else {
> > + data |=
> MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;
> > + data1 |= (DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK
> |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
> > + data2 |= (DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
> > + }
> >
> > if (def != data)
> > - WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
> > + WREG32_SOC15(MMHUB, 0,
> mmMM_ATC_L2_CGTT_CLK_CTRL, data);
> > + if (def1 != data1)
> > + WREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL,
> data1);
> > + if (def2 != data2)
> > + WREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL,
> data2);
> > }
> >
> > static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev, @@
> > -555,26 +580,39 @@ static int mmhub_v2_3_set_clockgating(struct
> > amdgpu_device *adev,
> >
> > static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev,
> > u32 *flags) {
> > - int data, data1;
> > + int data, data1, data2, data3;
> >
> > if (amdgpu_sriov_vf(adev))
> > *flags = 0;
> >
> > - data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
> > - data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
> > + data = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
> > + data1 = RREG32_SOC15(MMHUB, 0,
> mmMM_ATC_L2_CGTT_CLK_CTRL);
> > + data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL);
> > + data3 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL);
> >
> > /* AMD_CG_SUPPORT_MC_MGCG */
> > - if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
> > - !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
> > + if (!(data & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
> > DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
> > DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
> > DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
> > DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
> > - DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
> > - *flags |= AMD_CG_SUPPORT_MC_MGCG;
> > + DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))
> > + && !(data1 &
> MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK)) {
> > + *flags |= AMD_CG_SUPPORT_MC_MGCG;
> > + }
> >
> > /* AMD_CG_SUPPORT_MC_LS */
> > - if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
> > + if (!(data1 & MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK)
> > + && !(data2 &
> (DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
> > +
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK))
> > + && !(data3 &
> (DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
> > +
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK)))
> > *flags |= AMD_CG_SUPPORT_MC_LS;
> > }
> >
> > --
> > 2.25.1
> >
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